Generating integrated circuit placements using neural networks

US11556690B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11556690-B2
Application numberUS-202117555085-A
CountryUS
Kind codeB2
Filing dateDec 17, 2021
Priority dateApr 22, 2020
Publication dateJan 17, 2023
Grant dateJan 17, 2023

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Abstract

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Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

First claim

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What is claimed is: 1. A method of training a node placement neural network that comprises: an encoder neural network that is configured to, at each of a plurality of time steps, receive an input representation comprising data representing a current state of a placement of a netlist of nodes on a surface of an integrated circuit chip as of the time step and process the input representation to generate an encoder output, and a policy neural network configured to, at each of the plurality of time steps, receive an encoded representation generated from the encoder output generated by the encoder neural network and process the encoded representation to generate a score distribution over a plurality of positions on the surface of the integrated circuit chip, the method comprising: obtaining supervised training data comprising: a plurality of training input representations, each training input representation representing a respective placement of a respective netlist of nodes, and for each training input representation, a respective target value of a reward function that measures a quality of the placement of the respective netlist of nodes; and training the encoder neural network jointly with a reward prediction neural network on the supervised training data through supervised learning, wherein the reward prediction neural network is configured to, for each training encoder input, receive the encoder output generated by the encoder neural network from the training input representation and process the encoded representation to generate a predicted value of the reward function for the placement represented by the training input representation. 2. The method of claim 1 , further comprising: training the policy neural network through reinforcement learning to generate score distributions that result in placements that maximize the reward function. 3. The method of claim 2 , wherein training the policy neural network through reinforcement learning comprises holding values of parameters of the encoder neural network fixed during the training of the policy neural network through reinforcement learning. 4. The method of claim 1 , further comprising: after training the node placement neural network: receiving new netlist data; fine-tuning the trained node placement neural network on the new netlist data through reinforcement learning; and generating an integrated circuit placement for the new netlist data using the fine-tuned node placement neural network, comprising placing a respective node from the new netlist data at each of a plurality of time steps using score distributions generated by the fine-tuned node placement neural network. 5. The method of claim 1 , wherein the reward function includes a wire length term that measures a wire length of wires on the surface of the integrated circuit chip. 6. The method of claim 1 , wherein the reward function include a congestion term that measures congestion on the surface of the integrated circuit chip. 7. The method of claim 1 , wherein the reward function includes a timing term that measures a timing performance of the integrated circuit chip. 8. The method of claim 1 , further comprising: generating the supervised training data, comprising: obtaining data specifying a training accelerator netlist; generating a plurality of placements for the training accelerator netlist using a different policy neural network; and determining a respective value of the reward function for each of the plurality of placements for the training accelerator netlist. 9. A system comprising one or more computers and one or more storage devices storing instructions that when executed by the one or more computers cause the one or more computers to perform operations for training a node placement neural network that comprises: an encoder neural network that is configured to, at each of a plurality of time steps, receive an input representation comprising data representing a current state of a placement of a netlist of nodes on a surface of an integrated circuit chip as of the time step and process the input representation to generate an encoder output, and a policy neural network configured to, at each of the plurality of time steps, receive an encoded representation generated from the encoder output generated by the encoder neural network and process the encoded representation to generate a score distribution over a plurality of positions on the surface of the integrated circuit chip, the operations comprising: obtaining supervised training data comprising: a plurality of training input representations, each training input representation representing a respective placement of a respective netlist of nodes, and for each training input representation, a respective target value of a reward function that measures a quality of the placement of the respective netlist of nodes; and training the encoder neural network jointly with a reward prediction neural network on the supervised training data through supervised learning, wherein the reward prediction neural network is configured to, for each training encoder input, receive the encoder output generated by the encoder neural network from the training input representation and process the encoded representation to generate a predicted value of the reward function for the placement represented by the training input representation. 10. The system of claim 9 , the operations further comprising: training the policy neural network through reinforcement learning to generate score distributions that result in placements that maximize the reward function. 11. The system of claim 10 , wherein training the policy neural network through reinforcement learning comprises holding values of parameters of the encoder neural network fixed during the training of the policy neural network through reinforcement learning. 12. The system of claim 9 , the operations further comprising: after training the node placement neural network: receiving new netlist data; fine-tuning the trained node placement neural network on the new netlist data through reinforcement learning; and generating an integrated circuit placement for the new netlist data using the fine-tuned node placement neural network, comprising placing a respective node from the new netlist data at each of a plurality of time steps using score distributions generated by the fine-tuned node placement neural network. 13. The system of claim 9 , wherein the reward function includes a wire length term that measures a wire length of wires on the surface of the integrated circuit chip. 14. The system of claim 9 , wherein the reward function include a congestion term that measures congestion on the surface of the integrated circuit chip. 15. The system of claim 9 , wherein the reward function includes a timing term that measures a timing performance of the integrated circuit chip. 16. The system of claim 9 , the operations further comprising: generating the supervised training data, comprising: obtaining data specifying a training accelerator netlist; generating a plurality of placements for the training accelerator netlist using a different policy neural network; and determining a respective value of the reward function for each of the plurality of placements for the training accelerator netlist. 17. One or more non-transitory computer-readable storage media storing instructions that when executed by the one or more computers cause the one or more computers to perform operations for training a node placement neural network that comprises: an encoder n

Assignees

Inventors

Classifications

  • G06F30/392Primary

    Floor-planning or layout, e.g. partitioning or placement · CPC title

  • Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

  • G06F30/27Primary

    using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

  • Learning methods · CPC title

  • Auto-encoder networks; Encoder-decoder networks · CPC title

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What does patent US11556690B2 cover?
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each…
Who is the assignee on this patent?
Google Llc
What technology area does this patent fall under?
Primary CPC classification G06F30/392. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 17 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).