Generating integrated circuit placements using neural networks

US2023117786A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2023117786-A1
Application numberUS-202218082392-A
CountryUS
Kind codeA1
Filing dateDec 15, 2022
Priority dateApr 22, 2020
Publication dateApr 20, 2023
Grant date

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of training a node placement neural network that comprises: an encoder neural network that is configured to, at each of a plurality of time steps, receive an input representation comprising data representing a current state of a placement of a netlist of nodes on a surface of an integrated circuit chip as of the time step and process the input representation to generate an encoder output, and a policy neural network configured to, at each of the plurality of time steps, receive an encoded representation generated from the encoder output generated by the encoder neural network and process the encoded representation to generate a score distribution over a plurality of positions on the surface of the integrated circuit chip, the method comprising: obtaining supervised training data comprising: a plurality of training input representations, each training input representation representing a respective placement of a respective netlist of nodes, and for each training input representation, a respective target value of a reward function that measures a quality of the placement of the respective netlist of nodes; and training the encoder neural network jointly with a reward prediction neural network on the supervised training data through supervised learning, wherein the reward prediction neural network is configured to, for each training encoder input, receive the encoder output generated by the encoder neural network from the training input representation and process the encoded representation to generate a predicted value of the reward function for the placement represented by the training input representation.

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Classifications

  • Auto-encoder networks; Encoder-decoder networks · CPC title

  • Supervised learning · CPC title

  • Reinforcement learning · CPC title

  • Distributed learning, e.g. federated learning · CPC title

  • characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title

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What does patent US2023117786A1 cover?
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each…
Who is the assignee on this patent?
Google Llc
What technology area does this patent fall under?
Primary CPC classification G06F30/27. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Apr 20 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).