Storage device operation orchestration
US-12591382-B2 · Mar 31, 2026 · US
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Hush Glen E patents
Hush Glen E is listed as an inventor on 344 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hush Glen E |
| Total patents | 344 |
| First publication | Dec 10, 2015 |
| Latest publication | Mar 31, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Sense amplifiers as static random access memory
US-12572287-B2 · Mar 10, 2026 · US
Processing unit of memory for table lookup
US-2026056742-A1 · Feb 26, 2026 · US
Input/output connections of wafer-on-wafer bonded memory and logic
US-12555625-B2 · Feb 17, 2026 · US
A processing unit in memory for performing matrix-vector multiplication operations
US-2026030318-A1 · Jan 29, 2026 · US
Double bank prefetch
US-2026031117-A1 · Jan 29, 2026 · US
Row and column access of matrices stored in memory
US-2026031115-A1 · Jan 29, 2026 · US
Multiplexor for a processing unit of memory
US-2026023528-A1 · Jan 22, 2026 · US
Coupling processing units to data buses in memory
US-2026023695-A1 · Jan 22, 2026 · US
Multiplexor placement for implementing a processing unit in memory
US-2026024576-A1 · Jan 22, 2026 · US
Recent patents
Latest publications not already listed above.
Apparatuses and methods for data movement
US-12524175-B2 · Jan 13, 2026 · US
Signal routing between memory die and logic die for performing operations
US-2026011361-A1 · Jan 8, 2026 · US
Control logic in a memory device for generating internal commands
US-2026003519-A1 · Jan 1, 2026 · US
Address offset in memory
US-2025390227-A1 · Dec 25, 2025 · US
Apparatuses and methods for parallel writing to multiple memory device locations
US-2025362807-A1 · Nov 27, 2025 · US
Unauthorized memory access mitigation
US-2025284411-A1 · Sep 11, 2025 · US
Multiply-accumulate unit input mapping
US-2025278245-A1 · Sep 4, 2025 · US
Apparatuses and methods for ordering bits in a memory device
US-2025265091-A1 · Aug 21, 2025 · US
Apparatuses and methods for parallel writing to multiple memory device structures
US-12393342-B2 · Aug 19, 2025 · US
Testing memory of wafer-on-wafer bonded memory and logic
US-12387780-B2 · Aug 12, 2025 · US
Signal routing between memory die and logic die for performing operations
US-12354649-B2 · Jul 8, 2025 · US
On-die testing for a memory device
US-2025218526-A1 · Jul 3, 2025 · US
Apparatuses and methods for organizing data in a memory device
US-2025191969-A1 · Jun 12, 2025 · US
Unauthorized memory access mitigation
US-12321617-B2 · Jun 3, 2025 · US
Conditional write back scheme for memory
US-12322468-B2 · Jun 3, 2025 · US
Apparatuses and methods for ordering bits in a memory device
US-12314723-B2 · May 27, 2025 · US
Signal routing between memory die and logic die
US-2025104761-A1 · Mar 27, 2025 · US
Apparatuses and methods for operations in a self-refresh state
US-2025095708-A1 · Mar 20, 2025 · US
Apparatuses and methods for organizing data in a memory device
US-12249377-B2 · Mar 11, 2025 · US
Processing in memory registers
US-2025069629-A1 · Feb 27, 2025 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 322 |
| Lodestar Licensing Group Llc | 22 |
| Micro Tech Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C7/1006 | 213 |
| G11C11/4091 | 171 |
| G11C7/065 | 104 |
| G11C11/4096 | 98 |
| G11C11/4093 | 95 |