Sense amplifiers as static random access memory

Patent metadata

Field	Value
Publication number	US-12572287-B2
Application number	US-202418402990-A
Country	US
Kind code	B2
Filing date	Jan 3, 2024
Priority date	Jan 31, 2023
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) resource. For example, a memory array of a memory device can be coupled to sense amplifiers. The sense amplifiers can be electrically disconnected from digit lines of the memory array. Data can be stored in the sense amplifiers. The data can be communicated from the sense amplifiers to a processing device external to the memory array and the sense amplifiers. The sense amplifiers can receive data from the processing device and, when electrically disconnected from the number of digit lines, store the received data.

First claim

What is claimed is:

1 . An apparatus, comprising:
a memory array, wherein the memory array comprises a dynamic random access memory DRAM) array; and
a plurality of sense amplifiers coupled to the memory array and configured to:
electrically disconnect from a number of digit lines of the memory array;
when electrically disconnected from the number of digit lines, store first data;
communicate the first data to a processing device external to the memory array and the plurality of sense amplifiers;
receive second data from the processing device; and
when electrically disconnected from the number of digit lines, store the second data.

2 . The apparatus of claim 1 , wherein the processing device is on-chip with the memory array and the plurality of sense amplifiers.

3 . The apparatus of claim 1 , wherein the plurality of sense amplifiers are further configured to:
prior to a refresh of the memory array, transfer the first data from the plurality of sense amplifiers to a row of memory cells of the memory array; sense third data from the memory array in association with the refresh; and subsequent to the refresh, transfer the first data from the row of memory cells of the memory array to the plurality of sense amplifiers.

4 . The apparatus of claim 3 , wherein the row of memory cells of the memory array is dedicated to storage of data transferred from the plurality of sense amplifiers during refreshing of the memory array.

5 . The apparatus of claim 1 , wherein the first or second data represents at least one of a global variable, a stack, or an instruction for the processing device.

6 . A method, comprising:
storing first data in an array of memory cells having a plurality of sense amplifiers coupled thereto; operating the plurality of sense amplifiers in a first mode in association with sensing the first data stored in the array of memory cells; and operating the plurality of sense amplifiers in a second mode in which the plurality of sense amplifiers serve as a static random access memory (SRAM) array.

7 . The method of claim 6 , wherein the plurality of sense amplifiers are coupled to respective digit line pairs of the array of memory cells, and
wherein the method further comprises electrically disconnecting the plurality of sense amplifiers from the respective digit line pairs in association with operating the plurality of sense amplifiers in the second mode.

8 . The method of claim 7 , further comprising, in association with operating the plurality of sense amplifiers in the second mode:
receiving, by a memory device comprising the array of memory cells, second data from a host to which the array of memory cells is coupled; and storing the second data in the plurality of sense amplifiers.

9 . The method of claim 8 , wherein the array of memory cells is a dynamic random access memory (DRAM) array, and
wherein the method further comprises, in association with operating the plurality of sense amplifiers in the second mode, providing the second data from the plurality of sense amplifiers to the host in response to a host command.

10 . The method of claim 8 , further comprising, in association with operating the plurality of sense amplifiers in the first mode and performing a refresh operation on the first data stored in the array of memory cells:
copying the second data from the plurality of sense amplifiers to a row of the array of memory cells; operating the plurality of sense amplifiers to sense the first data; and writing the first data from the plurality of sense amplifiers back to the array of memory cells.

11 . The method of claim 10 , further comprising, subsequent to performing the refresh operation on the first data, copying the second data from the row of the array of memory cells back to the plurality of sense amplifiers.

12 . A system, comprising:
a memory device comprising a plurality of banks, each bank comprising a respective memory array coupled to a respective plurality of sense amplifiers; and a processing device that is on-chip with and coupled to the memory device, wherein each respective plurality of sense amplifiers is configured to:
in a first mode, electrically disconnect from a number of digit lines of the memory array;
in the first mode, receive first data from the processing device when electrically disconnected from the number of digit lines;
in the first mode, store the first data when electrically disconnected from the number of digit lines;
in the first mode, communicate second data to the processing device when electrically disconnected from the number of digit lines;
in a second mode, electrically connect to the number of digit lines of the memory array; and
in the second mode, sense third data from the memory array.

13 . The system of claim 12 , wherein the memory array comprises a dynamic random access memory (DRAM) array, and
wherein each respective plurality of sense amplifiers is further configured to, in the first mode, provide a capability associated with a static random access memory (SRAM) resource.

14 . The system of claim 13 , wherein each respective plurality of sense amplifiers is further configured to switch from the first mode to the second mode in advance of a refresh of the DRAM array.

15 . The system of claim 14 , wherein each respective plurality of sense amplifiers is further configured to, in the second mode:
transfer fourth data from the plurality of sense amplifiers to a plurality of memory cells of the DRAM array that is associated with a first address space of the DRAM array; and transfer, in advance of the refresh of the memory array, the first data from the plurality of sense amplifiers to a different plurality of memory cells of the DRAM array that are associated with a second address space of the DRAM array.

16 . The system of claim 15 , wherein each respective plurality of sense amplifiers is further configured to, in the second mode and subsequent to the refresh, transfer the first data from the different plurality of memory cells of the DRAM array to the plurality of sense amplifiers.

17 . The system of claim 15 , wherein the second address space is dedicated to storage of data transferred from the plurality of sense amplifiers during refreshing of the DRAM array.

18 . The system of claim 11 , wherein each respective plurality of sense amplifiers comprises a respective sense amplifier stripe of the plurality of banks.

19 . An apparatus, comprising:
a memory array; and a plurality of sense amplifiers coupled to the memory array and configured to:
electrically disconnect from a number of digit lines of the memory array;
when electrically disconnected from the number of digit lines, store first data;
communicate the first data to a processing device external to the memory array and the plurality of sense amplifiers;
receive second data from the processing device; and
when electrically disconnected from the number of digit lines, store the second data; and
wherein the plurality of sense amplifiers are further configured to:
prior to a refresh of the memory array, transfer the first data from the plurality of sense amplifiers to a row of memory cells of the memory array;
sense third data from the memory array in association with the refresh; and
subsequent to the refresh, transfer the first data from the row of memory cells of the memory array to the plurality of sense amplifiers.

20 . An apparatus, comprising:
a memory array; and a plurality of sens

Assignees

• Micron Technology Inc

Inventors

• Hush Glen E

Classifications

• G06F3/0629 Primary

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0626 Primary

  Reducing size or complexity of storage systems · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title