Apparatuses and methods for organizing data in a memory device

Patent metadata

Field	Value
Publication number	US-12249377-B2
Application number	US-202318225574-A
Country	US
Kind code	B2
Filing date	Jul 24, 2023
Priority date	Dec 21, 2018
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

First claim

What is claimed is:

1. An apparatus, comprising:
an array of memory cells;
a data interface;
a column decode circuitry coupled between the array of memory cells and the data interface; and
a controller coupled to the array of memory cells, the controller configured to cause the apparatus to:
perform a number of prefetch operations, wherein each of the number prefetch operations transfer a particular amount of data from the array of memory cells to a number of sense amplifiers and wherein the particular amount of data corresponds to an amount of data in a matrix having a matrix configuration; and
organize the particular amount of data to correspond to a portion of the matrix configuration by selecting a first portion of the particular amount of data to transfer from a number to sense amplifiers to a processing resource.

2. The apparatus of claim 1 , wherein the first portion of the particular amount of data corresponds to a row of the matrix configuration.

3. The apparatus of claim 1 , wherein the matrix configuration is stored in a register on the apparatus.

4. The apparatus of claim 1 , wherein the column decode circuitry is configured to send the first portion of the particular amount of data to the processing resource.

5. The apparatus of claim 1 , wherein the controller is further configured to cause the column code circuitry to select the first portion of the particular amount of data.

6. The apparatus of claim 1 , wherein a read operation stores the particular amount of data in the number of sense amplifiers.

7. The apparatus of claim 1 , wherein the controller configured to cause the apparatus to select a second portion of the particular amount of data that to corresponds to the matrix configuration.

8. The apparatus of claim 7 , wherein the second portion of the particular amount of data corresponds to a second row of the matrix configuration.

9. The apparatus of claim 7 , wherein the column decode circuitry is configured to send the second portion of the particular amount of data to the processing resource.

10. A method, comprising:
performing a number of prefetch operations, wherein each of the number prefetch operations transfer a particular amount of data from an array of memory cells to a number of sense amplifiers and wherein the particular amount of data corresponds to an amount of data in a matrix having a matrix configuration; and
organize the particular amount of data to correspond to a portion of the matrix configuration by selecting a first portion of the particular amount of data to transfer from the number to sense amplifiers to a processing resource.

11. The method of claim 10 , wherein selecting the first portion of the particular amount of data corresponds to a first row of the matrix configuration.

12. The method of claim 10 , wherein selecting the first portion of the particular amount of data corresponds to a first column of the matrix configuration.

13. The method of claim 10 , further including selecting a second portion of the particular amount of data to correspond to the matrix configuration to transfer from the number to sense amplifiers to the processing resource.

14. The method of claim 13 , wherein the second portion of the particular amount of data corresponds to a second row of the matrix configuration.

15. The method of claim 13 , wherein second portion of the particular amount of data corresponds to a second column of the matrix configuration.

16. A method, comprising:
performing a number of prefetch operations, wherein each of the number prefetch operations reads a particular amount of data from an array of memory cells on a memory device and stores the particular amount of data in a number of sense amplifiers on the memory device and wherein the particular amount of data corresponds to an amount of data in a matrix having a matrix configuration that is stored in a register of the memory device; and
selecting a first number of bits of the particular amount of data that correspond to a first portion of the matrix configuration to transfer from the number to sense amplifiers to a processing resource.

17. The method of claim 16 , wherein selecting the first number of bits includes selecting data stored in consecutive sense amplifiers.

18. The method of claim 17 , wherein the first number of bits corresponds to a first row of the matrix configuration.

19. The method of claim 16 , wherein selecting the first number of bits includes selecting data stored in every eighth sense amplifier starting with a first sense amplifier.

20. The method of claim 19 , wherein the first number of bits corresponds to a first column of the matrix configuration.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Hush Glen E
• Boehm Aaron P
• Luo Fa-Long

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P90/126

  by chemical etching · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10W10/0127

  using both n-type and p-type impurities, e.g. for isolation of complementary doped regions · CPC title