Testing memory of wafer-on-wafer bonded memory and logic

Patent metadata

Field	Value
Publication number	US-12387780-B2
Application number	US-202217885291-A
Country	US
Kind code	B2
Filing date	Aug 10, 2022
Priority date	Aug 10, 2021
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. Memory devices can be formed on a first wafer. First metal pads can be formed on the first wafer and coupled to the memory devices. The memory devices can be tested via the first metal pads. The first metal pads can be removed from the first wafer. Subsequently, second metal pads on the first wafer can be bonded, via a wafer-on-wafer bonding process, to third metal pads on a second wafer. Each memory device on the first wafer can be aligned with and coupled to a respective logic device on the second wafer.

First claim

What is claimed is:

1. A method, comprising:
forming a plurality of memory devices on a first wafer;
forming a plurality of first metal pads on the first wafer and coupled to the plurality of memory devices;
testing the plurality of memory devices via the plurality of first metal pads to yield results comprising respective values of a performance metric;
removing the plurality of first metal pads from the first wafer;
subsequent to removing the plurality of first metal pads:
bonding, via a wafer-on-wafer bonding process, a plurality of second metal pads on the first wafer to a plurality of third metal pads on a second wafer such that each of the plurality of memory devices on the first wafer is aligned with and coupled to at least a respective one of a plurality of logic devices on the second wafer;
singulating the bonded first and second wafers into individual wafer-on-wafer bonded memory and logic dies;
subsequent to singulating the bonded first and second wafers:
using a first subset of the individual wafer-on-wafer bonded memory to logic dies as a first component of a memory system in response to the first subset having a first value of the performance metric; and
using a second subset of the individual wafer-on-wafer bonded memory and logic dies as a second component of the memory system in response to the second subset having a second value of the performance metric.

2. The method of claim 1 , further comprising discarding a third subset of the individual wafer-on-wafer bonded memory and logic dies in response to the third subset having a third value of the performance metric.

3. The method of claim 1 , wherein forming the plurality of first metal pads comprises:
forming a material on the wafer; and
forming the plurality of first metal pads in the material, and
wherein removing the plurality of first metal pads comprises removing the material from the first wafer.

4. The method of claim 1 , further comprising, prior to the wafer-on-wafer bonding process, forming the plurality of third metal pads on the second wafer.

5. The method of claim 4 , wherein forming the plurality of third metal pads comprises forming logic-to-memory circuitry on the plurality of logic devices.

6. The method of claim 1 , further comprising, prior to the wafer-on-wafer bonding process, forming the plurality of logic devices on the second wafer.

7. The method of claim 1 , further comprising, prior to the wafer-on-wafer bonding process, forming the plurality of second metal pads on the first wafer.

8. The method of claim 7 , wherein forming the plurality of second metal pads comprises forming memory-to-logic circuitry on the plurality of memory devices.

9. The method of claim 8 , wherein forming the memory-to-logic circuitry further comprises coupling a plurality of local input/output (LIO) lines of the memory devices to a subset of the second metal pads and to a different subset of the second metal pads,
wherein the subset of the second metal pads are dedicated to communication between the plurality of memory devices and the plurality of logic devices via the memory-to-logic circuitry, and
wherein the different subset of the second metal pads are dedicated to communication external to the wafer-on-wafer bonded memory dies and logic dies.

10. The method of claim 1 , wherein bonding the second metal pads to the plurality of third metal pads comprises coupling a respective input/output (IO) line of each of the plurality of memory devices to an IO line of a respective one of the plurality of logic devices.

11. A method, comprising:
testing a memory device of a memory die formed on a first wafer via a metal pad in a material of the first wafer, wherein the memory die comprises a plurality of input/output (IO) lines coupled to the memory device;
subsequent to testing the memory device, removing the material from the first wafer;
subsequent to removing the material from the first wafer, forming a wafer-on-wafer bond between the first wafer and a second wafer having a logic die formed thereon,
wherein forming the wafer-on-wafer bond comprises:
providing a plurality of data paths from the memory die directly to the logic die, and
coupling the plurality of IO lines to a deep learning accelerator (DLA) formed on the logic die.

12. The method of claim 11 , further comprising, prior to forming the wafer-on-wafer bond, positioning the first wafer and the second wafer such that the memory die and the logic die are in a face-to-face arrangement; and
forming the wafer-on-wafer bond such that the memory die and the logic die remain in the face-to-face arrangement.

13. The method of claim 11 , wherein forming the wafer-on-wafer bond comprises forming a metal material in contact with the memory die and the logic die.

14. The method of claim 11 , wherein forming the wafer-on-wafer bond comprises bonding a first metal material of the logic die to a second metal material of the memory die.

15. The method of claim 14 , wherein bonding the first metal material and the second metal material comprises merging, via a thermal process, the first metal material and the second metal material into a third metal material in contact with the memory die and the logic die.

16. A method, comprising:
testing a plurality of memory dies formed on a wafer via a plurality of metal pads in a material of the wafer;
subsequent to testing the plurality of memory dies, removing the material and the plurality of metal pads from the wafer;
subsequent to removing the material from the wafer, singulating the wafer into a plurality of individual memory dies comprising a first memory die and a second memory die;
communicatively coupling, in a face-to-face arrangement, the first memory die to a deep learning accelerator (DLA) on a logic die, wherein the DLA is distinct from other circuitry of the logic die; and
communicatively coupling, in the face-to-face arrangement, the second memory die to the other circuitry of the logic die,
wherein the first memory die has a more preferred result from the testing of the plurality of memory dies and the second memory die has a less preferred result from the testing of the plurality of memory dies.

17. The method of claim 16 , wherein testing the plurality of memory dies comprises, prior to singulating the wafer into the plurality of individual memory dies:
determining that the first memory die has the more preferred result; and
determining that the second memory die has the less preferred result.

18. The method of claim 17 , further comprising:
communicatively coupling the first memory die to the DLA in response to determining that the first memory die has the more preferred result; and
communicatively coupling the second memory die to the other circuitry of the logic die in response to determining that the second memory die has the less preferred result.

19. The method of claim 16 , further comprising selecting the first memory die from a first subset of the plurality of individual memory dies having the more preferred result.

20. The method of claim 16 , further comprising selecting the second memory die from a second subset of the plurality of individual memory dies having the less preferred result.

Assignees

• Micron Technology Inc

Inventors

• Parekh Kunal R
• Hush Glen E
• Eilert Sean S
• Zaidy Aliasger T

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/01

  Manufacture or treatment · CPC title