Apparatuses and methods for data movement

Patent metadata

Field	Value
Publication number	US-12524175-B2
Application number	US-202418751917-A
Country	US
Kind code	B2
Filing date	Jun 24, 2024
Priority date	Feb 17, 2016
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

First claim

What is claimed is:

1 . An apparatus, comprising:
a first logic coupled to a first array portion and configured to perform a first operation on first data values stored in memory cells of the first array portion using a first compute component coupled to the first array portion; and a second logic coupled to a second array portion and configured to perform a second operation on second data values stored in memory cells of the second array portion using a second compute component coupled to the second array portion; and wherein data values corresponding to respective results of the first operation are moved from the first compute component to the second array portion prior to performance of the second operation.

2 . The apparatus of claim 1 , wherein the first logic and the second logic comprise separate subarray controllers.

3 . The apparatus of claim 1 , wherein the first operation and the second operation comprise different logical operations.

4 . The apparatus of claim 1 , wherein the apparatus further comprises a controller coupled to the first logic and to the second logic, and wherein the controller is configured to execute host commands.

5 . The apparatus of claim 4 , further comprising a shared I/O line configured to move the data values corresponding to the respective results of the first operation from the first compute component to the second array portion.

6 . The apparatus of claim 5 , wherein the controller is configured to move, from the first compute component to a particular row of the second array portion, the data values corresponding to the respective results of the first operation.

7 . The apparatus of claim 5 , wherein the first array portion and the second array portion correspond to different subarrays of an array of memory cells comprising a plurality of subarrays.

8 . The apparatus of claim 5 , wherein the controller is configured to execute DRAM commands received from a host.

9 . A method, comprising:
performing, via a first logic coupled to a first array portion, a first operation on first data stored in a first group of memory cells; and performing, via a second logic coupled to a second array portion, a second operation on second data stored in a second group of memory cells; wherein the first operation and the second operation are executed independently by the respective first and second logics; wherein the first operation and the second operation are operations in a sequence of operations performed on data stored in the respective first and second groups of memory cells; and wherein the first operation and the second operation are performed using respective compute components coupled to the first and the second array portions.

10 . The method of claim 9 , further comprising:
executing a first set of instructions received by the first logic to perform the first operation; and executing a second set of instructions received by the second logic to perform the second operation.

11 . The method of claim 10 , further comprising receiving the first set of instructions and the second set of instructions from a host.

12 . The method of claim 9 , wherein the respective first and second groups of memory cells correspond to respective different subarrays of an array of memory cells.

13 . The method of claim 9 , further comprising moving data values corresponding to respective results of the first operation from a first compute component coupled to the first array portion to the second group of memory cells prior to performing the second operation.

14 . The method of claim 9 , wherein performing the first operation comprises performing a particular logical operation, and wherein performing the second operation comprises performing a different particular logical operation.

15 . A method, comprising:
performing, via a first compute component, a first operation on first data stored in a first group of memory cells of a first array portion; and performing, via a second compute component, a second operation on second data stored in a second group of memory cells of a second array portion; wherein the first operation and the second operation are executed independently by the respective first and second compute components; and wherein the first operation and the second operation are operations in a sequence of operations performed on data stored in the respective first and second groups of memory cells.

16 . The method of claim 15 , wherein the first compute component and the second compute component serve as respective accumulators.

17 . The method of claim 15 , wherein the first array portion and the second array portion comprise respective subarrays.

18 . The method of claim 17 , wherein the first array portion and the second array portion are in different banks.

19 . The method of claim 15 , wherein the method includes performing the sequence of operations in association with systolic movement of data stored in an array of memory cells comprising the first array portion and the second array portion.

20 . The method of claim 15 , wherein the first array portion and the second array portion are coupled to respective different first and second controllers, and wherein the method includes controlling execution of the first and the second operations via the respective first and second controllers.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Lea Perry V
• Hush Glen E

Classifications

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G11C2207/2245

  Memory devices with an internal cache buffer · CPC title