Package comprising an interconnection die located between substrates
US-12500187-B2 · Dec 16, 2025 · US
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Hsu Marcus patents
Hsu Marcus is listed as an inventor on 20 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hsu Marcus |
| Total patents | 20 |
| First publication | Dec 6, 2018 |
| Latest publication | Dec 16, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Package comprising an interconnection die located between substrates
US-2023369261-A1 · Nov 16, 2023 · US
Package comprising a substrate with a bump pad interconnect comprising a trapezoid shaped cross section
US-2023352390-A1 · Nov 2, 2023 · US
Redistribution layer connection
US-11784151-B2 · Oct 10, 2023 · US
Package having a substrate comprising surface interconnects aligned with a surface of the substrate
US-11682607-B2 · Jun 20, 2023 · US
Passive component embedded in an embedded trace substrate (ETS)
US-11552023-B2 · Jan 10, 2023 · US
Bump pad structure
US-11527498-B2 · Dec 13, 2022 · US
Package comprising integrated devices coupled through a bridge
US-2022375838-A1 · Nov 24, 2022 · US
Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods
US-11456291-B2 · Sep 27, 2022 · US
Package having a substrate comprising surface interconnects aligned with a surface of the substrate
US-2022246496-A1 · Aug 4, 2022 · US
Recent patents
Latest publications not already listed above.
Package comprising a substrate configured as a heat spreader
US-11404343-B2 · Aug 2, 2022 · US
Bump pad structure
US-2022102298-A1 · Mar 31, 2022 · US
Redistribution layer connection
US-2022028816-A1 · Jan 27, 2022 · US
Integrated circuit (ic) packages employing split, double-sided metallization structures to facilitate a semiconductor die ("die") module employing stacked dice, and related fabrication methods
US-2021407979-A1 · Dec 30, 2021 · US
Passive component embedded in an embedded trace substrate (ets)
US-2021407918-A1 · Dec 30, 2021 · US
Integrated circuit (ic) packages employing split, double-sided metallization structures to facilitate a semiconductor die ("die") module employing stacked dice, and related fabrication methods
US-2021280523-A1 · Sep 9, 2021 · US
Package comprising a substrate configured as a heat spreader
US-2021249325-A1 · Aug 12, 2021 · US
High density embedded interconnects in substrate
US-10804195-B2 · Oct 13, 2020 · US
High density embedded interconnects in substrate
US-2020051907-A1 · Feb 13, 2020 · US
Symmetric embedded trace substrate
US-2018350630-A1 · Dec 6, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 20 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/701 | 16 |
| H10W70/65 | 13 |
| H10W70/685 | 11 |
| H10W90/724 | 11 |
| H10W90/00 | 10 |