Bump pad structure

Patent metadata

Field	Value
Publication number	US-11527498-B2
Application number	US-202017038124-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Sep 30, 2020
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

Aspects disclosed herein include a device including a bump pad structure and methods for fabricating the same. The device includes a bump pad. The device also includes a first trace adjacent the bump pad, where a first trace top surface is recessed a first recess distance from a bump pad top surface. The device also includes a second trace adjacent the first trace, covered at least in part by a solder resist. The device also includes a substrate, where the bump pad, the first trace, and the second trace are each formed on a portion of the substrate.

First claim

What is claimed is:

1. A device, comprising:
a bump pad;
a first trace adjacent the bump pad, wherein a first trace top surface is recessed a first recess distance from a bump pad top surface;
a second trace adjacent the first trace, covered at least in part by a solder resist, wherein the first trace is disposed between the bump pad and the second trace; and
a substrate, wherein the bump pad, the first trace, and the second trace are each formed on a portion of the substrate, wherein the bump pad, the first trace, and the second trace are each embedded in the substrate.

2. The device of claim 1 , further comprising:
a plurality of bump pads formed in a bumping region of the substrate;
a plurality of first traces formed in an open region of the substrate; and
a plurality of second traces covered at least in part by a solder resist formed in a solder resist region of the substrate,
wherein the open region is located on both sides of the bumping region, and wherein the solder resist region is located on each side of the open region opposite the bumping region.

3. The device of claim 1 , wherein the bump pad is recessed from a top surface of the substrate by a first depth.

4. The device of claim 3 , wherein the first depth is in a range of 1 um to 3 um.

5. The device of claim 3 , wherein the first trace is recessed from the top surface of the substrate by a second depth.

6. The device of claim 5 , wherein the second depth is in a range of 3 um to 7 um.

7. The device of claim 6 , wherein the first recess distance is a difference between the second depth and the first depth.

8. The device of claim 1 , wherein a top surface of the bump pad and a top surface of the first trace have less surface roughness than a top surface of the second trace.

9. The device of claim 8 , wherein the top surface of the bump pad and the top surface of the first trace each have a maximum roughness average of 200 nm and the top surface of the second trace has a maximum roughness average of 550 nm.

10. A device, comprising:
a bump pad;
a first trace adjacent the bump pad, wherein a first trace top surface is recessed a first recess distance from a bump pad top surface;
a second trace adjacent the first trace, covered at least in part by a solder resist, wherein the first trace is disposed between the bump pad and the second trace; and

a substrate, wherein the bump pad, the first trace, and the second trace are each formed on a portion of the substrate, wherein the bump pad, the first trace, and the second trace are each formed on a top surface of the substrate.

11. The device of claim 10 , wherein the bump pad has a pad thickness measured from a top surface of the substrate.

12. The device of claim 11 , wherein the pad thickness is in a range of 9 um to 12 um.

13. The device of claim 11 , wherein the first trace has a first thickness measured from the top surface of the substrate.

14. The device of claim 13 , wherein the first thickness is in a range of 6 um to 9 um.

15. The device of claim 13 , wherein the first recess distance is a difference between the pad thickness and the first thickness.

16. The device of claim 10 , further comprising:
a seed layer disposed on the substrate, wherein the seed layer forms part of the bump pad, the first trace and the second trace.

17. The device of claim 16 , further comprising:
a base metal layer disposed on the substrate, wherein the seed layer is deposited on the base metal layer.

18. The device of claim 16 , further comprising:
a primer layer disposed on the substrate, wherein the seed layer is deposited on the primer layer.

19. The device of claim 1 , wherein the device is a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, or an automotive vehicle.

20. A method of fabricating a device, comprising:
forming a bump pad;
forming a first trace adjacent the bump pad, wherein a first trace top surface is recessed a first recess distance from a bump pad top surface;
forming a second trace adjacent the first trace, covered at least in part by a solder resist, wherein the first trace is disposed between the bump pad and the second trace; and
providing a substrate, wherein the bump pad, the first trace, and the second trace are each formed on a portion of the substrate,

wherein forming the bump pad, the first trace and the second trace comprise:
forming a mask over the bump pad; and
performing a first etching process, wherein the first etching process reduces a thickness of the first trace and a thickness of the second trace.

21. The method of claim 20 , further comprising:
forming a plurality of bump pads in a bumping region of the substrate;
forming a plurality of first traces in an open region of the substrate; and
forming a plurality of second traces covered at least in part by a solder resist in a solder resist region of the substrate,
wherein the open region is located on both sides of the bumping region, and wherein the solder resist region is located on each side of the open region opposite the bumping region.

22. The method of claim 20 , wherein forming the bump pad, the first trace and the second trace further comprises:
stripping the mask from the bump pad;
performing a roughing process to roughen exposed surfaces of the bump pad, the first trace and the second trace; and
depositing the solder resist to the second trace.

23. The method of claim 20 , wherein forming the bump pad, the first trace and the second trace further comprises:
performing a second etching process, wherein the second etching process reduces the thickness of the first trace and a thickness of the bump pad to form the first recess distance.

24. The method of claim 23 , wherein a top surface of the bump pad and a top surface of the first trace have less surface roughness than a top surface of the second trace due to the second etching process.

25. The method of claim 24 , wherein the top surface of the bump pad and the top surface of the first trace each have a maximum roughness average of 200 nm and the top surface of the second trace has a maximum roughness average of 550 nm.

26. The method of claim 20 , wherein the bump pad, the first trace, and the second trace are each embedded in the substrate.

27. The method of claim 20 , wherein the bump pad, the first trace, and the second trace are each formed on a top surface of the substrate.

28. A device, comprising:
a bump pad;
a first trace adjacent the bump pad, wherein a first trace top surface is recessed a first recess distance from a bump pad top surface;
a second trace adjacent the first trace, covered at least in part by a solder resist; and
a substrate, wherein the bump pad, the first trace, and the second trace are each formed on a portion of the substrate and wherein a top surface of the bump pad and a top surface of the first trace have less surface roughness than a top surface of the second trace.

Assignees

• Qualcomm Inc

Inventors

• Kang Kuiwon
• Kim Michelle Yejin
• Hsu Marcus

Classifications

• H10W70/6565

  recessed into the surface of the package substrates, interposers, or redistribution layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title