Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods

Patent metadata

Field	Value
Publication number	US-11456291-B2
Application number	US-202016910486-A
Country	US
Kind code	B2
Filing date	Jun 24, 2020
Priority date	Jun 24, 2020
Publication date	Sep 27, 2022
Grant date	Sep 27, 2022

Abstract

Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.

First claim

What is claimed is:

1. An integrated circuit (IC) package, comprising:
a first metallization structure comprising at least one first interconnect layer;
a second metallization structure comprising at least one second interconnect layer; and
an IC die module disposed between the first metallization structure and the second metallization structure, the IC die module comprising:
a first IC die comprising a first active surface and a first non-active surface;
a second IC die comprising a second active surface and a second non-active surface; and
a compression bond between the first non-active surface of the first IC die and the second non-active surface of the second IC die coupling the first non-active surface of the first IC die to the second non-active surface of the second IC die;
the first active surface of the first IC die is electrically coupled to a first interconnect layer of the at least one first interconnect layer of the first metallization structure; and
the second active surface of the second IC die is electrically coupled to a second interconnect layer of the at least one second interconnect layer of the second metallization structure.

2. The IC package of claim 1 , wherein:
the first metallization structure is disposed in a first horizontal plane;
the second metallization structure is disposed in a second horizontal plane parallel to the first horizontal plane;
the first IC die is disposed in a third horizontal plane parallel to the first horizontal plane; and
the second IC die is disposed in the second horizontal plane parallel to the first horizontal plane.

3. The IC package of claim 1 , wherein:
the first metallization structure comprises a first redistribution layer (RDL) structure; and
the second metallization structure comprises a second RDL structure.

4. The IC package of claim 1 , wherein:
the first metallization structure comprises a first package substrate; and
the second metallization structure comprises a second package substrate.

5. The IC package of claim 1 , wherein:
the first active surface of the first IC die comprises a first bottom, active surface;
the first non-active surface of the first IC die comprises a first top, non-active surface;
the second active surface of the second IC die comprises a second bottom, active surface; and
the second non-active surface of the second IC die comprises a second top, non-active surface.

6. The IC package of claim 1 , wherein:
the first IC die further comprises at least one first die interconnect exposed at the first active surface;
the second IC die further comprises at least one second die interconnect exposed at the second active surface; and
further comprising:
a first compression bond between the at least one first die interconnect and the first metallization structure electrically coupling the at least one first die interconnect to the at least one first interconnect layer; and
a second compression bond between the at least one second die interconnect and the second metallization structure coupling the at least one second die interconnect to the at least one second interconnect layer.

7. The IC package of claim 6 , wherein:
the first metallization structure further comprises at least one first substrate interconnect electrically coupled to the at least one first interconnect layer;
the second metallization structure further comprises at least one second substrate interconnect electrically coupled to the at least one second interconnect layer;
the at least one first die interconnect is electrically coupled to the at least one first substrate interconnect to electrically couple the at least one first die interconnect to the at least one first interconnect layer; and
the at least one second die interconnect is electrically coupled to the at least one second substrate interconnect to electrically couple the at least one second die interconnect to the at least one second interconnect layer.

8. The IC package of claim 2 , wherein:
a height between a first outer surface of the first metallization structure and a first inside surface of the first metallization structure in a height axis direction perpendicular to the first horizontal plane is between fifteen (15) micrometers (μm) and 150 μm; and
a second height between a second outer surface of the second metallization structure and a second inside surface of the second metallization structure in the height axis direction perpendicular to the first horizontal plane is between fifteen (15) μm and 150 μm.

9. The IC package of claim 8 , wherein a third height of the IC die module between a first inside surface of the first metallization structure and a second inside surface of the second metallization structure in the height axis direction perpendicular to the first horizontal plane is between 100 μm and 600 μm.

10. The IC package of claim 1 , wherein:
the IC die module further comprises a third IC die comprising a third active surface and a third non-active surface;
a compression bond between the third non-active surface of the third IC die and the first non-active surface of the first IC die coupling the third non-active surface of the first IC die to the first non-active surface of the first IC die; and
the third active surface of the third IC die is electrically coupled to the at least one second interconnect layer of the second metallization structure.

11. The IC package of claim 10 , wherein:
the third IC die further comprises at least one third die interconnect exposed at the third active surface; and
further comprising:
a third compression bond between the at least one third die interconnect and the second metallization structure electrically coupling the at least one third die interconnect to the at least one second interconnect layer.

12. The IC package of claim 1 , wherein the IC die module further comprises at least one passive electrical device disposed adjacent to the first IC die and the second IC die;
the at least one passive electrical device electrically coupled to a first interconnect layer of the at least one first interconnect layer of the first metallization structure, and a second interconnect layer of the at least one second interconnect layer of the second metallization structure.

13. The IC package of claim 1 , wherein the IC die module further comprises at least one vertical interconnect access (via) disposed adjacent to the first IC die and the second IC die;
the at least one via electrically coupled to at least one first interconnect layer of the first metallization structure, and at least one second interconnect layer of the second metallization structure.

14. The IC package of claim 1 , further comprising at least one solder bump electrically coupled to at least one first interconnect layer of the first metallization structure.

15. The IC package of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player;

Assignees

• Qualcomm Inc

Inventors

• We Hong Bok
• Hsu Marcus
• Patil Aniket

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07332

  Compression bonding, e.g. thermocompression bonding · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W72/07307

  the auxiliary member being a temporary substrate, e.g. a removable substrate · CPC title