Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register
US-10628316-B2 · Apr 21, 2020 · US
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Hillman Daniel patents
Hillman Daniel is listed as an inventor on 16 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hillman Daniel |
| Total patents | 16 |
| First publication | May 3, 2018 |
| Latest publication | Apr 21, 2020 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank
US-10460781-B2 · Oct 29, 2019 · US
Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers
US-10446210-B2 · Oct 15, 2019 · US
Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register
US-10437491-B2 · Oct 8, 2019 · US
Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device
US-10437723-B2 · Oct 8, 2019 · US
Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device
US-10360964-B2 · Jul 23, 2019 · US
Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers
US-10192601-B2 · Jan 29, 2019 · US
Smart cache design to prevent overflow for a memory device with a dynamic redundancy register
US-10192602-B2 · Jan 29, 2019 · US
Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers
US-2018122449-A1 · May 3, 2018 · US
Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers
US-2018122448-A1 · May 3, 2018 · US
Recent patents
Latest publications not already listed above.
Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device
US-2018122447-A1 · May 3, 2018 · US
Smart cache design to prevent overflow for a memory device with a dynamic redundancy register
US-2018122450-A1 · May 3, 2018 · US
Memory device with a dual y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank
US-2018122446-A1 · May 3, 2018 · US
Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register
US-2018121361-A1 · May 3, 2018 · US
Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device
US-2018121355-A1 · May 3, 2018 · US
Method of processing incompleted memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register
US-2018121117-A1 · May 3, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Spin Transfer Tech Inc | 16 |
| Spin Memory Inc | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/1675 | 14 |
| G11C11/1677 | 14 |
| G11C11/1673 | 12 |
| G11C7/1039 | 12 |
| G11C11/1697 | 8 |