Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register

Patent metadata

Field	Value
Publication number	US-10628316-B2
Application number	US-201715855907-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Sep 27, 2016
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A memory device for storing data is disclosed. The memory device comprises a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells. The memory device also comprises a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks. Further, the device comprises a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

First claim

We claim:

1. A memory device for storing data, the memory device comprising:
a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells;
a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks, and wherein each pipeline is configured to process write operations of a first plurality of data words addressed to its associated memory bank; and
a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

2. A memory device as described in claim 1 , wherein said addressable memory cells of said associated memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells.

3. A memory device as described in claim 1 , wherein each pipeline is operable to flush a currently processing first memory operation to an associated cache memory if a second memory operation that enters the pipeline has a different row address as the first memory operation.

4. A memory device as described in claim 1 , wherein each cache memory comprises one or more status indicators for indicating a partial occupancy level of said cache memory.

5. A memory device as described in claim 1 , wherein each pipeline supports multiple write attempts for a given write operation.

6. A memory device as described in claim 1 , wherein each pipeline supports a pre-read operation for a given write operation.

7. A memory device for storing data, the memory device comprising:
a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells;
a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks, and wherein each pipeline is configured to process write operations of a first plurality of data words addressed to its associated memory bank; and
a cache memory associated with each of the plurality of memory banks and each of the plurality of pipelines, and wherein the cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of the associated memory bank.

8. A memory device as described in claim 7 , wherein said addressable memory cells of said associated memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells.

9. A memory device as described in claim 7 , wherein each pipeline is operable to flush a currently processing first memory operation to the cache memory if a second memory operation that enters the pipeline has a different row address as the first memory operation.

10. A memory device as described in claim 7 , wherein the cache memory comprises one or more status indicators for indicating a partial occupancy level of the cache memory.

11. A memory device as described in claim 7 , wherein each pipeline supports multiple write attempts for a given write operation.

12. A memory device as described in claim 7 , wherein each pipeline supports a pre-read operation for a given write operation.

13. A memory device for storing data, the memory device comprising:
a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells, wherein the addressable memory cells of an associated memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells;
a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks, and wherein each pipeline is configured to process write operations of a first plurality of data words addressed to its associated memory bank; and
a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

14. A memory device as described in claim 13 , wherein each pipeline is operable to flush a currently processing first memory operation to an associated cache memory if a second memory operation that enters the pipeline has a different row address as the first memory operation.

15. A memory device as described in claim 13 , wherein each cache memory comprises one or more status indicators for indicating a partial occupancy level of said cache memory.

16. A memory device as described in claim 13 , wherein each pipeline supports multiple write attempts for a given write operation.

17. A memory device as described in claim 13 , wherein each pipeline supports a pre-read operation for a given write operation.

Assignees

• Spin Transfer Tech Inc
• Spin Memory Inc

Inventors

• Berger Neal
• Louie Benjamin
• El-Baraji Mourad
• Crudele Lester
• Hillman Daniel

Classifications

• G11C11/1697

  Power supply circuits · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/1677

  Verifying circuits or methods · CPC title