Smart cache design to prevent overflow for a memory device with a dynamic redundancy register

Patent metadata

Field	Value
Publication number	US-10192602-B2
Application number	US-201715855855-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Sep 27, 2016
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a plurality of addressable memory cells configured in a plurality of segments wherein each segment contains N rows per segment, wherein the memory bank comprises a total of B entries, and wherein the memory cells are characterized by having a prescribed word error rate, E. Further, the device comprises a pipeline comprising M pipestages and configured to process write operations of a plurality of data words addressed to a given segment of the memory bank. The device also comprises a cache memory comprising Y number of entries, the cache memory associated with the given segment of the memory bank, and wherein the Y number of entries is based on the M, the N and the prescribed word error rate, E, to prevent overflow of the cache memory.

First claim

We claim:

1. A memory device for storing data, the memory device comprising:
a memory bank comprising a plurality of addressable memory cells configured in a plurality of segments wherein each segment contains N rows per segment, wherein the memory bank comprises a total of B entries, and wherein said memory cells are characterized by having a prescribed word error rate, E;
a pipeline comprising M pipestages and configured to process write operations of a first plurality of data words addressed to a given segment of said memory bank; and
a cache memory comprising Y number of entries, said cache memory associated with said given segment of said memory bank wherein said cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said given segment of said memory bank or is to be re-written into said given segment of said memory bank, and wherein said Y number of entries is based on said M, said N and said prescribed word error rate, E, to prevent overflow of said cache memory.

2. A memory device as described in claim 1 wherein said Y number of entries is at least (N*M+B*E) entries.

3. A memory device as described in claim 1 wherein said memory cells of said memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells.

4. A memory device as described in claim 1 wherein said given segment of said memory bank addresses a word using a common row address and discrete bit line column addresses.

5. A memory device as described in claim 1 further comprising:
a plurality of pipelines; and
a plurality of cache memories, and wherein further each segment of said plurality of segments has associated therewith a respective pipeline of said plurality of pipelines and a respective cache memory of said plurality of cache memories.

6. A memory device as described in claim 1 wherein M=2 and wherein E=1.

7. A memory device as described in claim 1 wherein said pipeline is operable to flush a currently processing first memory operation to said cache memory if a second memory operation enters said pipeline with a different row address than said first memory operation.

8. A memory device as described in claim 1 wherein said cache memory comprises one or more status indicators for indicating a partial occupancy level of said cache memory.

9. A memory device as described in claim 1 wherein said pipeline supports multiple write attempts for a given write operation.

10. A memory device as described in claim 1 wherein said pipeline supports a pre-read operation for a given write operation.

11. A memory device for storing data, the memory device comprising:
a memory bank comprising a plurality of addressable memory cells of row and bit lines and further configured in a plurality of segments wherein each segment contains N rows per segment and wherein words are addressed by a common row line and a plurality of bit lines and wherein said memory bank is characterized by having a prescribed word error rate, E, and wherein the memory bank comprises a total of B entries;
a pipeline comprising M pipestages and configured to process read operations and write operations of a first plurality of data words addressed to a given segment of said memory bank; and
a cache memory comprising Y number of entries, said cache memory associated with said given segment of said memory bank and wherein said cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said given segment of said memory bank or is to be re-written into said given segment of said memory bank, and wherein said Y number of entries is based on said M, said N and said prescribed word error rate, E, to prevent overflow of said cache memory.

12. A memory device as described in claim 11 wherein said Y number of entries is at least (N*M)+(B*E) entries.

13. A memory device as described in claim 12 wherein said memory cells of said memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells.

14. A memory device as described in claim 13 wherein said given segment of said memory bank addresses a word by using a common row address and by using discrete bit line addresses.

15. A memory device as described in claim 13 further comprising:
a plurality of pipelines; and
a plurality of cache memories, and wherein further each segment of said plurality of segments has associated therewith a respective pipeline of said plurality of pipelines and a respective cache memory of said plurality of cache memories.

16. A memory device as described in claim 11 wherein M=2 and wherein E=1.

17. A memory device as described in claim 13 wherein said pipeline is operable to flush a currently processing first memory operation to said cache memory if a second memory operation enters said pipeline having a different row address as said first memory operation.

18. A memory device as described in claim 11 wherein said cache memory comprises status indicators for indicating a partial occupancy level of said cache memory.

19. A memory device as described in claim 11 wherein said pipeline supports multiple write attempts for a given write operation.

20. A memory device as described in claim 11 wherein said pipeline supports a pre-read operation for a given write operation.

21. A method of writing data within a memory device, the method comprising:
processing write operations using a pipeline wherein said pipeline is operable to process said write operations to write data to a memory bank, wherein said processing comprises transferring write operations to a cache memory that require one of: write verification; and subsequent write processing;
storing a write operation in a vacant entry of said cache memory that requires one of: write verification; and subsequent write processing through said pipeline;
removing a write operation from said cache memory that write verifies; and
removing a write operation from said cache memory that is re-written to said memory bank, and
wherein said memory bank comprises a plurality of addressable memory cells of N word row lines wherein words are addressed by a common word row line and a plurality of bit column lines, wherein said memory bank is characterized by having a prescribed word error rate, E, and wherein the memory bank comprises a total of B entries, and
wherein said pipeline comprises M pipestages, and
wherein said cache memory comprises Y number of entries, wherein said Y number of entries is based on said M, said N and said prescribed word error rate, E, to prevent overflow of said cache memory.

22. A method as described in claim 21 wherein said Y number of entries is at least (N*M)+(B*E) entries.

23. A method as described in claim 21 wherein said memory cells of said memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells.

Assignees

• Spin Transfer Tech Inc

Inventors

• Berger Neal
• Louie Benjamin
• El-Baraji Mourad
• Crudele Lester
• Hillman Daniel

Classifications

• G11C11/1657

  Word-line or row circuits · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/1677

  Verifying circuits or methods · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title