Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device

Patent metadata

Field	Value
Publication number	US-10360964-B2
Application number	US-201715855589-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Sep 27, 2016
Publication date	Jul 23, 2019
Grant date	Jul 23, 2019

Abstract

A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words and associated memory addresses into a cache memory, and wherein each data word of the second plurality of data words is associated with a pending operation. Additionally, the method comprises detecting a power up signal and responsive to the power up signal, transferring the second plurality of data words and associated memory addresses from the secure memory storage area to the cache memory. Finally, responsive to the transferring, and before the memory device is powered up, the method comprises processing the second plurality of data words and associated memory addresses from the cache memory to the pipeline for writing data to the memory bank during power up.

First claim

We claim:

1. A method of writing data into a memory device, the method comprising:
utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank;
writing a second plurality of data words and associated memory addresses into a cache memory, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank;
detecting a power down signal;
responsive to the power down signal, transferring the second plurality of data words and associated memory addresses from said cache memory into a secure memory storage area in the memory bank;
detecting a power up signal;
responsive to the power up signal, and before said memory device is powered up, transferring the second plurality of data words and associated memory addresses from said secure memory storage area to said cache memory; and
responsive to the transferring, and before said memory device is powered up, processing the second plurality of data words and associated memory addresses from said cache memory to said pipeline for writing data to the memory bank during power up.

2. A method as described in claim 1 wherein said memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.

3. A method as described in claim 1 further comprising:
responsive to said power down signal, transferring any partially completed write operations of said pipeline to said secure memory storage area.

4. A method as described in claim 1 further comprising:
responsive to said power down signal, copying any partially completed write operations of said pipeline to said cache memory.

5. A method as described in claim 1 wherein said transferring comprise utilizing a secure communication process substantially compliant with one of: voting; ECC encoding; use of multiple copies; comparing multiple copies; and voting from multiple copies.

6. A method as described in claim 1 wherein said power down signal originates from a system level software stack and represents a system wide orderly power down event.

7. A method as described in claim 1 further comprising removing a data word and its associated address from said cache memory responsive to an indication that said data word has been verified as properly written to said memory bank.

8. A method of writing data into a memory device, the method comprising:
utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank;
writing a second plurality of data words and associated memory addresses into a cache memory, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank;
detecting a power down signal;
responsive to the power down signal, transferring the second plurality of data words and associated memory addresses from said cache memory into a secure memory storage area in the memory bank;
detecting a power up signal; and
responsive to the power up signal, and before said memory device is powered up, transferring the second plurality of data words and associated memory addresses from said secure memory storage area to said pipeline for writing data to the memory bank during power up.

9. A method as described in claim 8 wherein said memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.

10. A method as described in claim 8 further comprising:
responsive to said power down signal, transferring any partially completed write operations of said pipeline to said secure memory storage area.

11. A method as described in claim 8 further comprising:
responsive to said power down signal, copying any partially completed write operations of said pipeline to said cache memory.

12. A method as described in claim 8 wherein said transferring comprise utilizing a secure communication process substantially compliant with one of: voting; ECC encoding; use of multiple copies; comparing multiple copies; and voting from multiple copies.

13. A method as described in claim 8 wherein said power down signal originates from a system level software stack and represents a system wide orderly power down event.

14. A method as described in claim 8 further comprising removing a data word and its associated address from said cache memory responsive to an indication that said data word has been verified as properly written to said memory bank.

15. A memory device for storing data, the memory device comprising:
a memory bank comprising a plurality of addressable memory cells;
a pipeline configured to process write operations of a first plurality of data words addressed to said memory bank;
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank; and
a logic module operable to:
detect a power down signal;
responsive to the power down signal, transfer the second plurality of data words and associated memory addresses from said cache memory into a secure memory storage area reserved in the memory bank;
detect a power up signal;
responsive to said power up signal, and before said memory device is powered up, transfer data words and associated memory addresses from said secure memory storage area to said cache memory; and
before said memory device is powered up, process said data words and associated memory addresses from said cache memory to said pipeline for storage to said memory bank during power up.

16. A memory device as described in claim 15 wherein said plurality of addressable memory cells of said memory bank comprises spin-transfer torque magnetic random access memory (STT-MRAM) cells.

17. A memory device as described in claim 15 wherein said logic module utilizes a secure communication process substantially compliant with one of: voting; ECC encoding; use of multiple copies; comparing multiple copies; and voting from multiple copies.

18. A memory device as described in claim 15 wherein a data word and its associated address are removed from said cache memory responsive to an indication that said data word has been verified as properly written to said memory bank.

19. A memory device for storing data, the memory device comprising:
a memory bank comprising a plurality of addressable memory cells;
a pipeline configured to process write operations of a first plurality of data words addressed to said memory bank;
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank; and
a logic module operable to:
detect a power down signal;
responsive to the power down signal, transfer the second plurality of data words and associated memory addresses from said cache memory into a secure memory storage area reserved in the mem

Assignees

• Spin Transfer Tech Inc
• Spin Memory Inc

Inventors

• Berger Neal
• Louie Benjamin
• El-Baraji Mourad
• Crudele Lester
• Hillman Daniel

Classifications

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C14/0081

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/1653

  Address circuits or decoders · CPC title