Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register

Patent metadata

Field	Value
Publication number	US-10437491-B2
Application number	US-201715855263-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Sep 27, 2016
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. Further, the method comprises writing a second plurality of data words and associated memory addresses into a cache memory, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The method also comprises detecting a power down signal and responsive to the power down signal, transferring the second plurality of data words and associated memory addresses from the cache memory into a secure memory storage area reserved in the memory bank. Finally, the method comprises powering down the memory device.

First claim

We claim:

1. A method of writing data into a memory device, the method comprising:
utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank;
writing a second plurality of data words and associated memory addresses into a cache memory, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank;
detecting a power down signal;
responsive to the power down signal, transferring the second plurality of data words and associated memory addresses from said cache memory into a secure memory storage area reserved in the memory bank; and
powering down the memory device.

2. A method as described in claim 1 wherein said memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.

3. A method as described in claim 1 further comprising: responsive to said power down signal, transferring any partially completed write operations of said pipeline to said secure memory storage area.

4. A method as described in claim 1 further comprising: responsive to said power down signal, and before said transferring, copying any partially completed write operations of said pipeline to said cache memory.

5. A method as described in claim 1 wherein said transferring comprises utilizing a secure communication process substantially compliant with one of: voting; ECC encoding; use of multiple copies; comparing multiple copies; and voting from multiple copies.

6. A method as described in claim 1 wherein said power down signal originates from a system level software stack and represents a system wide orderly power down event.

7. A method as described in claim 1 further comprising removing a data word and its associated address from said cache memory responsive to an indication that said data word has been verified as properly written to said memory bank.

8. A method as described in claim 1 , further comprising:
receiving a power up signal;
responsive to the power up signal, transferring the second plurality of data words and associated memory addresses from the secure memory storage area to the cache memory; and
processing said second plurality of data words, from said cache memory, through said pipeline for writing into said memory bank.

9. A memory device for storing data, the memory device comprising:
a memory bank comprising a plurality of addressable memory cells;
a pipeline configured to process write operations of a first plurality of data words addressed to said memory bank;
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank; and
a logic module operable to:
detect a power down signal;
responsive to the power down signal, transfer the second plurality of data words and associated memory addresses from said cache memory into a secure memory storage area reserved in the memory bank; and
power down the memory device.

10. A memory device as described in claim 9 wherein said plurality of addressable memory cells of said memory bank comprises spin-transfer torque magnetic random access memory (STT-MRAM) cells.

11. A memory device as described in claim 9 wherein said logic module is further operable to, responsive to said power down signal, transfer any partially completed write operations of said pipeline to said secure memory storage area.

12. A memory device as described in claim 9 wherein said logic module is further operable to, responsive to said power down signal, and before said transfer, copy any partially completed write operations of said pipeline to said cache memory.

13. A memory device as described in claim 9 wherein said logic module utilizes a secure communication process substantially compliant with one of: voting; ECC encoding; use of multiple copies; comparing multiple copies; and voting from multiple copies.

14. A memory device as described in claim 9 wherein said power down signal originates from a system level software stack and represents a system wide orderly power down event.

15. A memory device as described in claim 9 wherein a data word and its associated address are removed from said cache memory responsive to an indication that said data word has been verified as properly written to said memory bank.

16. A memory device as described in claim 9 wherein said logic module is further operable to:
detect a power up signal;
responsive to the power up signal, transfer the second plurality of data words and associated memory addresses from the secure memory storage area to the cache memory; and
cause said pipeline to process said second plurality of data words, from said cache memory, for writing into said memory bank.

17. A memory device for storing data, the memory device comprising:
a memory bank comprising a plurality of addressable memory cells;
a pipeline configured to process write operations of a first plurality of data words addressed to said memory bank;
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank; and
a logic module operable to:
detect a power up signal;
responsive to the power up signal, transfer the second plurality of data words and associated memory addresses from said a secure memory storage area to said cache memory; and
cause said pipeline to process said second plurality of data words, from said cache memory, for writing into said memory bank.

18. A memory device as described in claim 17 wherein said plurality of addressable memory cells of said memory bank comprises spin-transfer torque magnetic random access memory (STT-MRAM) cells.

19. A memory device as described in claim 17 wherein said power signal is generated in response to an initiation of a power up process and wherein further said pipeline is operable to process said second plurality of data words, during said power up process.

20. A memory device as described in claim 17 wherein said memory bank comprises said secure memory storage area.

Assignees

• Spin Transfer Tech Inc
• Spin Memory Inc

Inventors

• Berger Neal
• Louie Benjamin
• El-Baraji Mourad
• Crudele Lester
• Hillman Daniel

Classifications

• G06F2212/1052

  Security improvement · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F12/0855

  Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence) · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title