Cryptographic computing engine for memory load and store units of a microarchitecture pipeline

Patent metadata

Field	Value
Publication number	US-11575504-B2
Application number	US-202016776467-A
Country	US
Kind code	B2
Filing date	Jan 29, 2020
Priority date	Jun 29, 2019
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

A processor comprises a first register to store an encoded pointer to a memory location. First context information is stored in first bits of the encoded pointer and a slice of a linear address of the memory location is stored in second bits of the encoded pointer. The processor also includes circuitry to execute a memory access instruction to obtain a physical address of the memory location, access encrypted data at the memory location, derive a first tweak based at least in part on the encoded pointer, and generate a keystream based on the first tweak and a key. The circuitry is to further execute the memory access instruction to store state information associated with memory access instruction in a first buffer, and to decrypt the encrypted data based on the keystream. The keystream is to be generated at least partly in parallel with accessing the encrypted data.

First claim

What is claimed is:

1. A processor, comprising:
a first register to store an encoded pointer to a memory location, wherein first context information is stored in first bits of the encoded pointer and a slice of a linear address of the memory location is stored in second bits of the encoded pointer; and
circuitry to execute a memory access instruction to:
access encrypted data at the memory location;
derive a first tweak based at least in part on the encoded pointer;
generate a keystream based on the first tweak and a first key;
and
decrypt the encrypted data based on the keystream, wherein the keystream is to be generated at least partly in parallel with accessing the encrypted data.

2. The processor of claim 1 , wherein the circuitry is to execute the memory access instruction to further:
store, in a first buffer, state information associated with the memory access instruction, wherein the state information includes the encoded pointer, the keystream, the first context information, and an identifier associated with the memory access instruction.

3. The processor of claim 2 , wherein the first buffer further includes the linear address of the memory location, a size of data requested by the memory access instruction, and the encrypted data.

4. The processor of claim 2 , further comprising:
a second buffer to store the linear address, a size of data requested by the memory access instruction, the identifier associated with the memory access instruction, and the encrypted data.

5. The processor of claim 1 , wherein the circuitry is to execute the memory access instruction to further:
search a translation lookaside buffer (TLB) based on the encoded pointer;
determine that a physical address of the memory location is mapped to the encoded pointer in the TLB; and
retrieve the physical address from the TLB.

6. The processor of claim 1 , wherein the circuitry is to execute the memory access instruction to further:
identify a plaintext portion of the linear address stored in the encoded pointer;
search a translation lookaside buffer (TLB) based on the plaintext portion of the linear address;
identify a speculative linear address based, at least in part, on a portion of the speculative linear address matching the plaintext portion of the linear address stored in the encoded pointer;
retrieve a speculative physical address mapped to the speculative linear address in the TLB;
decode the encoded pointer to obtain a decoded linear address; and
compare the speculative linear address to the decoded linear address to determine whether to perform a new search in the TLB based on the decoded linear address.

7. The processor of claim 6 , wherein the circuitry is to execute the memory access instruction to further:
cease pipeline operations associated with the speculative linear address in response to a determination that the speculative linear address does not match the decoded linear address.

8. The processor of claim 7 , wherein the circuitry is to execute the memory access instruction to further:
perform a second search in the TLB using the decoded linear address;
identify a matching linear address, wherein the matching linear address is mapped to a physical address of the memory location; and
retrieve the physical address from the TLB.

9. The processor of claim 6 , wherein the circuitry is to execute the memory access instruction to further:
allow pipeline operations associated with the speculative linear address to continue in response to a determination that the speculative linear address does match the decoded linear address.

10. The processor of claim 9 , wherein the pipeline operations include using the speculative physical address to access the encrypted data at the memory location.

11. The processor of claim 6 , wherein the slice of the linear address stored in the second bits of the encoded pointer includes the plaintext portion of the linear address.

12. The processor of claim 6 , wherein the plaintext portion of the linear address is stored externally to the encoded pointer.

13. The processor of claim 1 , further comprising:
a store buffer to temporarily store data to be stored to memory, wherein the circuitry is to execute a second memory access instruction for a second encoded pointer to a second memory location, to:
search the store buffer based on the second encoded pointer;
identify a matching encoded pointer based on the search; and
retrieve second data indexed by the matching encoded pointer from the store buffer.

14. The processor of claim 13 , wherein the circuitry is to execute the second memory access instruction to further:
derive a second tweak based at least in part on the second encoded pointer;
generate a second keystream based on the second tweak and a second key; and
decrypt the second data based on the keystream.

15. The processor of claim 1 , further comprising:
a store buffer to temporarily store data to be stored to memory, wherein the circuitry is to execute a third memory access instruction for a third encoded pointer to a third memory location, to:
identify a plaintext portion of a third linear address stored in the third encoded pointer;
search the store buffer based on the plaintext portion of the third linear address;
identify a speculative encoded pointer based, at least in part, on a portion of the speculative encoded pointer matching the plaintext portion of the third linear address; and
in response to identifying the speculative encoded pointer, determine whether the speculative encoded pointer corresponds to the third encoded pointer.

16. The processor of claim 15 , wherein the circuitry is to execute the third memory access instruction to further:
retrieve third data indexed by the speculative encoded pointer in response to determining that the speculative encoded pointer corresponds to the third encoded pointer.

17. The processor of claim 15 , wherein the circuitry is to execute the third memory access instruction to further:
obtain a second physical address for the third memory location from a translation lookaside buffer (TLB) in response to determining that the speculative encoded pointer does not correspond to the third encoded pointer;
access second encrypted data at the third memory location; and
decrypt the second encrypted data based on a second tweak and the first key.

18. The processor of claim 1 , wherein to decrypt the encrypted data based on the keystream is to include:
merging the keystream and the encrypted data using one of an exclusive-or (XOR) operation or a logic function including a plurality of logic operations.

19. The processor of claim 1 , wherein the circuitry is to execute the memory access instruction to further:
prior to generating the keystream, search a cache unit based on the encoded pointer to determine whether the encoded pointer is mapped to a precomputed keystream, wherein the keystream is generated in response to determining that the encoded pointer is not mapped to any of the precomputed keystreams stored in the cache unit.

20. A non-transitory machine-readable medium with code stored thereon, wherein the code is executable to cause a machine to:
store, in a register, an encoded pointer to a memory location, wherein first context information is stored in first bits of the encoded pointer and a slice of a linear address of the memory location is stored in second bits of the encoded pointer; and
execute a memory access instruction to:
access encrypted data at the memory location

Assignees

• Intel Corp

Inventors

• Durham David M
• Lemay Michael
• Kounavis Michael E
• Ghosh Santosh
• Deutsch Sergej
• Nori Anant Vithal
• Gaur Jayesh
• Subramoney Sreenivas
• Grewal Karanvir S

Classifications

• G06F21/602 Primary

  Providing cryptographic facilities or services · CPC title

• G06F2212/681

  Multi-level TLB, e.g. microTLB and main TLB · CPC title

• G06F2212/1052

  Security improvement · CPC title

• H04L9/0656

  Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher · CPC title

• H04L2209/125

  Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations · CPC title