Application programming interface for fine grained low latency decompression within processor core

Patent metadata

Field	Value
Publication number	US-12028094-B2
Application number	US-202017133622-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

Methods and apparatus relating to an Application Programming Interface (API) for fine grained low latency decompression within a processor core are described. In an embodiment, a decompression Application Programming Interface (API) receives an input handle to a data object. The data object includes compressed data and metadata. Decompression Engine (DE) circuitry decompresses the compressed data to generate uncompressed data. The DE circuitry decompress the compressed data in response to invocation of a decompression instruction by the decompression API. The metadata comprises a first operand to indicate a location of the compressed data, a second operand to indicate a size of the compressed data, a third operand to indicate a location to which decompressed data by the DE circuitry is to be stored, and a fourth operand to indicate a size of the decompressed data. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
memory to store a decompression Application Programming Interface (API), the decompression API to receive an input handle to a data object, wherein the data object includes compressed data and metadata; and
Decompression Engine (DE) circuitry to decompress the compressed data to generate uncompressed data, the DE circuitry to decompress the compressed data in response to invocation of a decompression instruction by the decompression API,
wherein the metadata comprises a first operand to indicate a location of the compressed data, a second operand to indicate a size of the compressed data, a third operand to indicate a location to which decompressed data by the DE circuitry is to be stored, and a fourth operand to indicate a size of the decompressed data.

2. The apparatus of claim 1 , wherein a compression API is to provide the second operand.

3. The apparatus of claim 2 , wherein the memory is to store the compression API.

4. The apparatus of claim 1 , wherein a compression API is to compress input data to generate the compressed data.

5. The apparatus of claim 4 , wherein the compression API is to compress the input data in accordance with a deflate function.

6. The apparatus of claim 4 , wherein the compression API is to insert the compressed data and the metadata into the data object.

7. The apparatus of claim 1 , wherein the DE circuitry is to decompress the compressed data in accordance with the metadata.

8. The apparatus of claim 1 , wherein the decompression instruction is to cause the DE circuitry to perform an out-of-order decompression of the plurality of cachelines.

9. The apparatus of claim 1 , wherein the DE circuitry is to inform a processor core after decompression of each one of one or more cachelines, wherein the one or more cachelines are to store the compressed data and/or the decompressed data.

10. The apparatus of claim 9 , wherein the DE circuitry is to inform the processor core via a dedicated signal, modification to a status bit in a register, or modification of a status bit in a cache coupled to the processor core.

11. The apparatus of claim 1 , wherein one or more of the first operand and the third operand comprise a virtual memory address.

12. The apparatus of claim 1 , wherein a processor core, the DE circuitry, and the memory are on a single integrated circuit die.

13. The apparatus of claim 12 , wherein the processor core comprises a Graphics Processing Unit (GPU) core.

14. One or more non-transitory computer-readable media comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
cause a decompression Application Programming Interface (API) to receive an input handle to a data object, wherein the data object includes compressed data and metadata; and
cause Decompression Engine (DE) circuitry to decompress the compressed data to generate uncompressed data, the DE circuitry to decompress the compressed data in response to invocation of a decompression instruction by the decompression API,
wherein the metadata comprises a first operand to indicate a location of the compressed data, a second operand to indicate a size of the compressed data, a third operand to indicate a location to which decompressed data by the DE circuitry is to be stored, and a fourth operand to indicate a size of the decompressed data.

15. The one or more computer-readable media of claim 14 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause a compression API to provide the second operand.

16. The one or more computer-readable media of claim 15 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause storage of the compression API in memory.

17. The one or more computer-readable media of claim 14 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause a compression API to compress input data to generate the compressed data.

18. The one or more computer-readable media of claim 17 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the compression API to compress the input data in accordance with a deflate function.

19. The one or more computer-readable media of claim 17 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the compression API to insert the compressed data and the metadata into the data object.

20. The one or more computer-readable media of claim 14 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the DE circuitry to decompress the compressed data in accordance with the metadata.

21. The one or more computer-readable media of claim 14 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the DE circuitry to perform an out-of-order decompression of the plurality of cachelines.

22. The one or more computer-readable media of claim 14 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the DE circuitry to inform a processor core after decompression of each one of one or more cachelines, wherein the one or more cachelines are to store the compressed data and/or the decompressed data.

23. The one or more computer-readable media of claim 22 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause the DE circuitry to inform the processor core via a dedicated signal, modification to a status bit in a register, or modification of a status bit in a cache coupled to the processor core.

24. The one or more computer-readable media of claim 14 , wherein one or more of the first operand and the third operand comprise a virtual memory address.

Assignees

• Intel Corp

Inventors

• Gaur Jayesh
• Chauhan Adarsh
• Gopal Vinodh
• Shanbhogue Vedvyas
• Subramoney Sreenivas
• Feghali Wajdi

Classifications

• G06F9/541

  via adapters, e.g. between incompatible applications · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F2212/401

  Compressed data · CPC title

• G06F9/3867

  using instruction pipelines · CPC title