Data relocation for inline metadata

Patent metadata

Field	Value
Publication number	US-11972126-B2
Application number	US-202117472272-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Mar 26, 2021
Publication date	Apr 30, 2024
Grant date	Apr 30, 2024

Abstract

Technologies disclosed herein provide one example of a system that includes processor circuitry to be communicatively coupled to a memory circuitry. The processor circuitry is to receive a memory access request corresponding to an application for access to an address range in a memory allocation of the memory circuitry and to locate a metadata region within the memory allocation. The processor circuitry is also to, in response to a determination that the address range includes at least a portion of the metadata region, obtain first metadata stored in the metadata region, use the first metadata to determine an alternate memory address in a relocation region, and read, at the alternate memory address, displaced data from the portion of the metadata region included in the address range of the memory allocation. The address range includes one or more bytes of an expected allocation region of the memory allocation.

First claim

What is claimed:

1. A system, comprising:
processor circuitry communicatively coupled to a memory, wherein the processor circuitry is to:
receive a memory access request corresponding to an application for access to first data associated with an address range in a memory allocation allocated for the application, the address range including a first portion of the first data to be accessed and at least a portion of a metadata region of the memory allocation;
locate the metadata region within the memory allocation; and
based on the address range including at least a portion of the metadata region:
obtain first metadata stored in the metadata region;
use the first metadata to determine an alternate memory address in a relocation region; and
read, at the alternate memory address, displaced data having an original address in the portion of the metadata region included in the address range in the memory allocation.

2. The system of claim 1 , wherein the address range includes one or more bytes of an expected allocation region of the memory allocation.

3. The system of claim 1 , wherein the relocation region is located at an end portion of the memory allocation, at a beginning portion of the memory allocation, or in an area of the memory outside the memory allocation.

4. The system of claim 1 , wherein the first metadata stored in the metadata region includes upper bound information that indicates an upper boundary of the memory allocation or lower bound information that indicates a lower boundary of the memory allocation.

5. The system of claim 4 , wherein the relocation region is located within the memory allocation and is aligned with one of the upper boundary of the memory allocation or the lower boundary of the memory allocation.

6. The system of claim 1 , wherein to locate the metadata region within the memory allocation is to include:
determining a second memory address of the metadata region based on address bits in an encoded pointer associated with the memory access request, size metadata in the encoded pointer, and a size of the metadata region, wherein the metadata region is divided at a mid-point address of a slot of the memory to which the memory allocation is assigned.

7. The system of claim 6 , wherein the size metadata in the encoded pointer represents a power of two size of a slot of the memory to which the memory allocation is assigned.

8. The system of claim 1 , wherein the first metadata is one of:
upper bound information that indicates an upper boundary of the memory allocation;
lower bound information that indicates a lower boundary of the memory allocation;
an offset to the relocation region from a mid-point address of a slot of the memory to which the memory allocation is assigned;
a pointer to the relocation region; or
an index to the relocation region.

9. The system of claim 1 , wherein the processor circuitry is further to:
in response to a memory allocation request to allocate the memory based on a first allocation size, perform a memory allocation operation including:
increasing the first allocation size to an increased memory allocation size based on metadata to be stored in the metadata region of the memory allocation;
obtaining the memory allocation based on the increased memory allocation size; and
storing the first metadata in the metadata region.

10. The system of claim 9 , wherein the processor circuitry is further to:
receive a memory store request corresponding to the application to store the first data in the address range of the memory allocation;
identify a second portion of the first data to be displaced from the metadata region; and
store the second portion of the first data as the displaced data at the alternate memory address in the relocation region.

11. The system of claim 1 , wherein the processor circuitry is further to:
in response to a memory allocation request to allocate the memory circuitry based on a first allocation size, perform a memory allocation operation including:
obtaining the memory allocation based on the first allocation size;
obtaining the relocation region outside the memory allocation;
generating a redirection pointer to the relocation region; and
storing the redirection pointer in the metadata region.

12. The system of claim 11 , wherein the processor circuitry is further to:
receive a memory store request corresponding to the application to store the first data in the address range of the memory allocation;
identify a second portion of the first data to be displaced from the metadata region; and
use the redirection pointer to store the second portion of the first data as the displaced data at the alternate memory address in the relocation region.

13. The system of claim 1 , wherein the processor circuitry is further to:
in response to a determination that a beginning memory address of the address range is located prior to the metadata region, access the first portion of the first data prior to the metadata region based on the beginning memory address of the address range; and
generate reassembled data corresponding to the address range by concatenating at least the displaced data and the first portion of the first data.

14. The system of claim 1 , wherein the memory is to include:
a metadata cache indexed by a metadata cache set index; and
a data cache indexed by a data cache set index,
wherein the processor circuitry is further to:
search the metadata cache using the metadata cache set index to obtain the first metadata; and
search the data cache using the data cache set index to obtain the displaced data.

15. The system of claim 14 , wherein the metadata cache set index is to be calculated using a number of higher order bits in a second memory address of the metadata region.

16. The system of claim 1 , wherein the processor circuitry is further to:
obtain, from a translation lookaside buffer, a translated memory address corresponding to a beginning memory address of the address range; and
in response to a determination that the address range and the metadata region are co-located on a memory page, use the translated memory address to calculate another translated memory address of the metadata region.

17. A non-transitory machine-readable storage medium including instructions that, when executed by first circuitry including a processor and a memory controller, cause the first circuitry to perform operations comprising:
receiving a memory access request corresponding to an application for access to first data associated with an address range in a memory allocation allocated for the application, the address range including at least a portion of a metadata region and a first portion of the first data to be accessed;
locating the metadata region within the memory allocation; and
based on the address range including at least a portion of the metadata region:
obtaining first metadata stored in the metadata region;
determining an alternate memory address in a relocation region, the determining based, at least in part, on the first metadata; and
reading, at the alternate memory address, displaced data having an original address in the portion of the metadata region included in the address range in the memory allocation.

18. The non-transitory machine-readable storage medium of claim 17 , wherein the relocation region is located at an end portion of the memory allocation, at a beginning portion of the memory allocation, or in an area of memory outside the memory allocation.

19. The non-transitory machine-reada

Assignees

• Intel Corp

Inventors

• Durham David M
• Lemay Michael D
• Deutsch Sergej
• Rakshit Joydeep
• Nori Anant Vithal
• Gaur Jayesh
• Subramoney Sreenivas

Classifications

• G06F3/0631 Primary

  by allocating resources to storage systems · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title