Lock-stepping asynchronous logic
US-12019526-B2 · Jun 25, 2024 · US
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Ganesan Aditi R patents
Ganesan Aditi R is listed as an inventor on 7 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ganesan Aditi R |
| Total patents | 7 |
| First publication | Jul 5, 2016 |
| Latest publication | Jun 25, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Parity protection of control registers based on register bit positions
US-11947409-B2 · Apr 2, 2024 · US
Lock-stepping asynchonous logic
US-2023376389-A1 · Nov 23, 2023 · US
Parity protection of control registers
US-2023222026-A1 · Jul 13, 2023 · US
Error detection using a logical address key
US-9916254-B2 · Mar 13, 2018 · US
Error detection using a logical address key
US-2016283323-A1 · Sep 29, 2016 · US
Error detection using a logical address key
US-9384144-B1 · Jul 5, 2016 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Xilinx Inc | 4 |
| Sk Hynix Inc | 3 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F11/1016 | 3 |
| G06F11/1068 | 3 |
| G11C29/52 | 3 |
| G06F12/1009 | 3 |
| G06F2212/65 | 3 |