Lock-stepping asynchronous logic

Patent metadata

Field	Value
Publication number	US-12019526-B2
Application number	US-202217746843-A
Country	US
Kind code	B2
Filing date	May 17, 2022
Priority date	May 17, 2022
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Methods and systems to detect a metastable condition and suppress/mask a signal during the metastable condition. The metastable condition may arise from asynchronous sampling. Techniques disclosed herein may be configured to enable asynchronous lock-stepping, where outputs of redundant circuit blocks of a first clock domain are received at input nodes of a second clock domain. In the second clock domain, logic states at the input nodes are compared to detect errors, and results of the comparison are masked during transitions at the input nodes. Masking may be constrained to situations where logic states at the input nodes differ.

First claim

What is claimed is:

1. An apparatus, comprising:
circuitry configured to generate a mismatch control signal indicating when logic states at first and second input nodes differ from one another;
a metastable condition detection circuit configured to detect a metastable condition at the first and second input nodes; and
a mask circuit configured to selectively mask the mismatch control signal based on an output of the metastable condition detection circuit.

2. The apparatus of claim 1 , wherein the metastable condition detection circuit is further configured to detect the metastable condition based on logic state transitions at the first and second input nodes.

3. The apparatus of claim 1 , wherein the metastable condition detection circuit is further configured to detect the metastable condition when a logic state transition is detected at one or more of the first and second input nodes and the logic states at the first and second input nodes differ from one another.

4. The apparatus of claim 1 , wherein the mask circuit is further configured to:
control an output of the mask circuit based on the mismatch control signal when the output of the metastable condition detection circuit is inactive; and
set the mismatch control signal to a predetermined logic state when the output of the metastable condition detection circuit is active.

5. The apparatus of claim 1 , wherein the metastable condition detection circuit comprises:
first and second edge detectors, each having an input coupled to a respective one of the first and second input nodes.

6. The apparatus of claim 5 , wherein the metastable condition detection circuit further comprises:
an XOR gate having inputs coupled to outputs of the first and second edge detectors.

7. The apparatus of claim 6 , wherein the metastable condition detection circuit further comprises:
a window circuit configured to extend a duration time for which the outputs of the first and second edge detectors remain active.

8. The apparatus of claim 1 , wherein the mask circuit comprises a NOR gate configured to receive the mismatch control signal and the output of the metastable condition detection circuit.

9. An integrated circuit device, comprising:
a first circuit block configured to operate under control of a first clock domain; and
a second circuit block configured to operate under control of a second clock domain;
wherein the first circuit block comprises first and second synchronizers, each to synchronize a digital signal to the second clock domain; and
wherein the second circuit block comprises,
first and second input nodes, each to receive an output of a respective one of the first and second synchronizers,
a comparator to generate a mismatch control signal indicating when logic states at the first and second input nodes differ from one another,
a metastable condition detection circuit configured to detect a metastable condition at the first and second input nodes, and
a mask circuit configured to selectively mask the mismatch control signal based on an output of the metastable condition detection circuit.

10. The integrated circuit device of claim 9 , wherein the metastable condition detection circuit is further configured to detect the metastable condition based on logic state transitions at the first and second input nodes.

11. The integrated circuit device of claim 9 , wherein the metastable condition detection circuit is further configured to detect the metastable condition when a logic state transition is detected at one or more of the first and second input nodes and the logic states at the first and second input nodes differ from one another.

12. The integrated circuit device of claim 9 , wherein the mask circuit is further configured to:
control an output of the mask circuit based on the mismatch control signal when the output of the metastable condition detection circuit is inactive; and
set the mismatch control signal to a predetermined logic state when the output of the metastable condition detection circuit is active.

13. The integrated circuit device of claim 9 , wherein the metastable condition detection circuit comprises:
first and second edge detectors, each having an input coupled to a respective one of the first and second input nodes.

14. The integrated circuit device of claim 13 , wherein the metastable condition detection circuit further comprises:
an XOR gate having inputs coupled to outputs of the first and second edge detectors.

15. The integrated circuit device of claim 14 , wherein the metastable condition detection circuit further comprises:
a window circuit configured to extend a duration time for which the outputs of the first and second edge detectors remain active.

16. The integrated circuit device of claim 9 , wherein the mask circuit comprises a NOR gate configured to receive the mismatch control signal and the output of the metastable condition detection circuit.

17. A method, comprising:
generating a mismatch control signal indicating when logic states at first and second input nodes differ from one another;
detecting a metastable condition at the first and second nodes; and
masking the mismatch control signal during the metastable condition.

18. The method of claim 17 , wherein the detecting comprises:
detecting the metastable condition based on logic state transitions at the first and second input nodes.

19. The method of claim 17 , wherein the detecting comprises:
detecting the metastable condition when a logic state transition is detected at one or more of the first and second input nodes and the logic states at the first and second input nodes differ from one another.

20. The method of claim 17 , wherein the masking comprises:
controlling an output based on the mismatch control signal in the absence of the metastable condition; and
setting the mismatch control signal to a predetermined logic state during the metastable condition.

Assignees

• Xilinx Inc

Inventors

• Tran David
• Ganesan Aditi R
• Goyal Anurag

Classifications

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title

• G06F11/1679 Primary

  at clock signal level · CPC title