Parity protection of control registers based on register bit positions

Patent metadata

Field	Value
Publication number	US-11947409-B2
Application number	US-202217574340-A
Country	US
Kind code	B2
Filing date	Jan 12, 2022
Priority date	Jan 12, 2022
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.

First claim

What is claimed is:

1. An integrated circuit (IC) device comprising:
a plurality of registers; and
parity checking circuitry coupled to the plurality of registers and comprising:
a first parity circuit configured to receive first register values from the plurality of registers and determine a first value from the first register values, wherein the first register values correspond to first bits of two or more of the plurality of registers, and wherein the first register values have fewer bits than the plurality of registers;
a second parity circuit configured to receive second register values from the plurality of registers and determine a second value from the second register values, wherein the second register values correspond to second bits of the two or more of the plurality of registers; and
error detection circuitry configured to:
compare the first value and the second value to detect a first error within the plurality of registers; and
output an error signal indicating the first error.

2. The IC device of claim 1 , wherein the parity checking circuitry further comprises:
a third parity circuit configured to receive the first register values and determine a third value from the first register values; and
a fourth parity circuit configured to receive the second register values and determine a fourth value from the second register values, wherein the error detection circuitry is further configured to detect a second error within the parity checking circuitry based on the first value, the second value, the third value, and the fourth value.

3. The IC device of claim 2 , wherein the error detection circuitry is configured to detect the second error by:
generating a first signal based on a comparison of the first value and the second value;
generating a second signal based on a comparison of the third value and the fourth value; and
comparing the first signal and the second signal.

4. The IC device of claim 1 , wherein the first parity circuit is configured to determine the first value by applying a mask to the first register values to determine first intermediate values, wherein the mask includes mask values, and wherein each of the first register values corresponds to a respective one of the mask values.

5. The IC device of claim 4 , wherein the first parity circuit is further configured to determine the first value by:
determining a second intermediate value based on the first intermediate values; and
comparing the second intermediate value and a valid value.

6. The IC device of claim 1 , wherein the parity checking circuitry is configured to determine the first value based on a monitor enable signal.

7. The IC device of claim 1 , wherein the first value is determined during a first period and wherein the second value is determined during a second period, the first period and the second period being non-overlapping.

8. A method comprising:
determining, by a first parity circuit of parity checking circuitry of an integrated circuit (IC) device, a first value from first register values of a plurality of registers of the IC device, wherein the first register values correspond to first bits of two or more of the plurality of registers, and wherein the first register values have fewer bits than the plurality of registers;
determining, by a second parity circuit of the parity checking circuitry, a second value from second register values of the plurality of registers, wherein the second register values correspond to second bits of the two or more of the plurality of registers;
comparing the first and second values to determine a first error within the plurality of registers; and
outputting an error signal indicative of the first error.

9. The method of claim 8 further comprising:
determining, by a third parity circuit of the parity checking circuitry, a third value from the first register values;
determining, by a fourth parity circuit of the parity checking circuitry, a fourth value from the second register values; and
determining a second error within the parity checking circuitry based on the first value, the second value, the third value, and the fourth value.

10. The method of claim 9 , wherein determining the second error within comprises:
generating a first signal based on a comparison of the first value and the second value;
generating a second signal based on a comparison of the third value and the fourth value; and
comparing the first signal and the second signal.

11. The method of claim 8 , wherein determining the first value comprises applying a mask to the first register values to determine first intermediate values, wherein the mask includes mask values, and wherein each of the first register values corresponds to a respective one of the mask values.

12. The method of claim 11 , wherein determining the first value further comprises:
determining a second intermediate value based on the first intermediate values; and
comparing the second intermediate value and a valid value.

13. The method of claim 8 , wherein detecting the first value is based on a monitor enable signal.

14. The method of claim 8 , wherein the first value is determined during a first period, and wherein the second value is determined during a second period, the first period and the second period being non-overlapping.

15. A parity checking circuitry comprising:
a first parity circuit configured to receive first register values from a plurality of registers and determine a first value from the first register values, wherein the first register values correspond to first bits of two or more of the plurality of registers, and wherein the first register values have fewer bits than the plurality of registers;
a second parity circuit configured to receive second register values from the plurality of registers and determine a second value from the second register values, wherein the second register values correspond to second bits of the two or more of the plurality of registers; and
error detection circuitry configured to:
compare the first value and the second value to determine a first error within the plurality of registers; and
output an error signal indicating the first error.

16. The parity checking circuitry of claim 15 further comprising:
a third parity circuit configured to determine a third value from the first register values; and
a fourth parity circuit configured to determine a fourth value from the second register values, wherein the error detection circuitry is further configured to determine a second error within the parity checking circuitry based on the first value, the second value, the third value, and the fourth value.

17. The parity checking circuitry of claim 16 , wherein the error detection circuitry is configured to determine the second error by:
generating a first signal based on a comparison of the first value and the second value;
generating a second signal based on a comparison of the third value and the fourth value; and
comparing the first signal and the second signal.

18. The parity checking circuitry of claim 15 , wherein the first parity circuit is configured to determine the first value by applying a mask to the first register values to determine first intermediate values, wherein the mask includes mask values, and wherein each of the first register values corresponds to a respective one of the mask values.

19. The parity checking circuitry of claim 18 , wherein the first parity circuit is configured to determine the first value by:
determining a second intermediate value b

Assignees

• Xilinx Inc

Inventors

• Azad Sarosh I
• Ganesan Aditi R

Classifications

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0751 Primary

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F11/1032

  Simple parity · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title