Error detection using a logical address key

Patent metadata

Field	Value
Publication number	US-9916254-B2
Application number	US-201615171724-A
Country	US
Kind code	B2
Filing date	Jun 2, 2016
Priority date	Mar 25, 2014
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A logical address key is generated based at least in part on a logical address. Encoded data is generated by systematically error correction encoding the logical address key and write data. One or more physical addresses are determined that correspond to the logical address where the physical addresses that correspond to the logical address are dynamic. At the physical addresses, the encoded data is stored with the logical address key removed.

First claim

What is claimed is:

1. A system, comprising:
a logical address key generator configured to generate a logical address key based at least in part on a logical address;
an address map configured to determine one or more physical addresses that correspond to the logical address, wherein the physical addresses that correspond to the logical address are dynamic;
a storage interface configured to read data from the physical addresses;
an error correction decoder configured to perform error correction decoding on the read data, with the logical address key inserted, in order to produce at least a corrected data portion and a corrected logical address key portion;
a key comparator configured to determine if the corrected logical address key portion matches the logical address key; and
an interface configured to:
in the event error correction decoding is successful and the corrected logical address key portion matches the logical address key, output the corrected data portion; and
in the event error correction decoding is not successful or the corrected logical address key portion does not match the logical address key, flag an error.

2. The system of claim 1 , wherein the system includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

3. The system of claim 1 further comprising solid state storage, wherein the storage interface is further configured to read data from the solid state storage.

4. The system of claim 1 , wherein the logical address key is further based at least in part on metadata that is managed by a host.

5. The system of claim 1 , wherein:
the error correction decoder includes a soft-input error correction decoder; and
the logical address key generator is further configured to generate soft information for the logical address key.

6. The system of claim 5 , wherein the logical address key generator generates soft information for the logical address key that does not include a highest certainty.

7. A method, comprising:
generating a logical address key based at least in part on a logical address;
determining one or more physical addresses that correspond to the logical address, wherein the physical addresses that correspond to the logical address are dynamic;
reading data from the physical addresses;
using an error correction decoder to perform error correction decoding on the read data, with the logical address key inserted, in order to produce at least a corrected data portion and a corrected logical address key portion;
determining if the corrected logical address key portion matches the logical address key;
in the event error correction decoding is successful and the corrected logical address key portion matches the logical address key, outputting the corrected data portion; and
in the event error correction decoding is not successful or the corrected logical address key portion does not match the logical address key, flagging an error.

8. The method of claim 7 , wherein the method is performed by a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

9. The method of claim 7 , wherein the logical address key is further based at least in part on metadata that is managed by a host.

10. The method of claim 7 , wherein:
the error correction decoder includes a soft-input error correction decoder; and
generating a logical address key includes generating soft information for the logical address key.

11. The method of claim 10 , wherein the generated soft information for the logical address key does not include a highest certainty.

Assignees

• Sk Hynix Inc

Inventors

• Yeung Kwok Wah
• Marrow Marcus
• Ganesan Aditi R

Classifications

• G06F11/1016 Primary

  Error in accessing a memory location, i.e. addressing error · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title