Error detection using a logical address key

Patent metadata

Field	Value
Publication number	US-9384144-B1
Application number	US-201414550522-A
Country	US
Kind code	B1
Filing date	Nov 21, 2014
Priority date	Mar 25, 2014
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A logical address key is generated based at least in part on a logical address. Encoded data is generated by systematically error correction encoding the logical address key and write data. One or more physical addresses are determined that correspond to the logical address where the physical addresses that correspond to the logical address are dynamic. At the physical addresses, the encoded data is stored with the logical address key removed.

First claim

What is claimed is:

1. A system, comprising:
a logical address key generator configured to generate a logical address key based at least in part on a logical address;
an error correction encoder configured to generate encoded data by systematically error correction encoding the logical address key and write data;
an address map configured to determine one or more physical addresses that correspond to the logical address, wherein the physical addresses that correspond to the logical address are dynamic; and
a storage interface configured to store, at the physical addresses, the encoded data with the logical address key removed.

2. The system of claim 1 , wherein the system includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

3. The system of claim 1 further comprising solid state storage, wherein the storage interface is further configured to store the encoded data with the logical address key removed on the solid state storage.

4. The system of claim 1 , wherein the logical address key is further based at least in part on metadata that is managed by a host.

5. A method, comprising:
generating a logical address key based at least in part on a logical address;
using an error correction encoder to generate encoded data by systematically error correction encoding the logical address key and write data;
determining one or more physical addresses that correspond to the logical address, wherein the physical addresses that correspond to the logical address are dynamic; and
storing, at the physical addresses, the encoded data with the logical address key removed.

6. The method of claim 5 , wherein the method is performed by a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

7. The method of claim 5 , wherein the logical address key is further based at least in part on metadata that is managed by a host.

Assignees

• Sk Hynix Inc

Inventors

• Yeung Kwok Wah
• Marrow Marcus
• Ganesan Aditi R

Classifications

• G06F11/1016 Primary

  Error in accessing a memory location, i.e. addressing error · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title