Delayed Cache Entry Invalidation Update for Potential Overwrite Re-use
US-2026086944-A1 · Mar 26, 2026 · US
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Foo Yoong Chert patents
Foo Yoong Chert is listed as an inventor on 77 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Foo Yoong Chert |
| Total patents | 77 |
| First publication | Jun 18, 2015 |
| Latest publication | Mar 26, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Multi-output decoder for texture decompression
US-12488516-B2 · Dec 2, 2025 · US
Hardware Support for Conversion between Integer and Floating-Point Data
US-2025355665-A1 · Nov 20, 2025 · US
Scheduling Tasks Using Swap Flags
US-2025348313-A1 · Nov 13, 2025 · US
On-demand Memory Allocation
US-2025284644-A1 · Sep 11, 2025 · US
Color state techniques for graphics processors
US-12412233-B1 · Sep 9, 2025 · US
Hardware support for conversion between integer and floating-point data
US-12405786-B1 · Sep 2, 2025 · US
Hardware Support for Conversion between Integer and Floating-Point Data
US-2025272095-A1 · Aug 28, 2025 · US
Preemption techniques for memory-backed registers
US-12353330-B2 · Jul 8, 2025 · US
Tiled Processor Communication Fabric
US-2025124643-A1 · Apr 17, 2025 · US
Recent patents
Latest publications not already listed above.
On-demand memory allocation
US-12265474-B2 · Apr 1, 2025 · US
Cache Control to Preserve Register Data
US-2025094357-A1 · Mar 20, 2025 · US
Method and system for multisample antialiasing
US-2025061657-A1 · Feb 20, 2025 · US
Task execution in a simd processing unit with parallel groups of processing lanes
US-2025061536-A1 · Feb 20, 2025 · US
Multi-stage thread scheduling
US-12190151-B2 · Jan 7, 2025 · US
Cache control to preserve register data
US-12182037-B2 · Dec 31, 2024 · US
Method and system for multisample antialiasing
US-12159347-B2 · Dec 3, 2024 · US
Task execution in a SIMD processing unit with parallel groups of processing lanes
US-12112396-B2 · Oct 8, 2024 · US
Cache Control to Preserve Register Data
US-2024289282-A1 · Aug 29, 2024 · US
Multi-phased and multi-threaded program execution based on simd ratio
US-2024241751-A1 · Jul 18, 2024 · US
Cache footprint management
US-11947462-B1 · Apr 2, 2024 · US
Multi-phased and multi-threaded program execution based on SIMD ratio
US-11947999-B2 · Apr 2, 2024 · US
Tiled processor communication fabric
US-11941742-B2 · Mar 26, 2024 · US
Multi-output decoder for texture decompression
US-2024095975-A1 · Mar 21, 2024 · US
Multi-stage Thread Scheduling
US-2024095065-A1 · Mar 21, 2024 · US
Preemption Techniques for Memory-Backed Registers
US-2024095176-A1 · Mar 21, 2024 · US
On-demand Memory Allocation
US-2024045808-A1 · Feb 8, 2024 · US
Tiled Processor Communication Fabric
US-2023419585-A1 · Dec 28, 2023 · US
Task execution in a simd processing unit with parallel groups of processing lanes
US-2023394615-A1 · Dec 7, 2023 · US
Multi-output decoder for texture decompression
US-11836830-B2 · Dec 5, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Imagination Tech Ltd | 54 |
| Apple Inc | 23 |
| Foo Yoong Chert | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T1/20 | 34 |
| G06F9/3887 | 30 |
| G06F9/4881 | 26 |
| G06F9/3836 | 22 |
| G06F15/8007 | 21 |