Cache Control to Preserve Register Data

Patent metadata

Field	Value
Publication number	US-2025094357-A1
Application number	US-202418962158-A
Country	US
Kind code	A1
Filing date	Nov 27, 2024
Priority date	Feb 23, 2023
Publication date	Mar 20, 2025
Grant date	—

Abstract

Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

First claim

What is claimed is:

1 . An apparatus, comprising:
processor pipeline circuitry configured to perform operations on register operand data; control circuitry configured to provide memory backing for register operand data in a memory hierarchy, wherein the memory hierarchy includes:
a data cache;
an operand cache between the processor pipeline circuitry and the data cache in the memory hierarchy;
lock circuitry configured to:
control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated as being utilized by instructions of the first thread;
preserve register operand data in the data cache, including to prevent eviction of a given cache line from the data cache based on an asserted lock indicator for register data stored in the given cache line; and
in response to a reset event:
flush operand data to the memory hierarchy from one or more operand cache entries indicated as being last-use; and
clear the first set of lock indicators.

2 . The apparatus of claim 1 , wherein the lock circuitry is further configured to, in response to the reset event:
assert one or more lock indicators for the registers whose operand data was flushed from the one or more operand cache entries.

3 . The apparatus of claim 2 , wherein, to assert the one or more lock indicators for the registers whose operand data was flushed from the one or more operand cache entries, the lock circuitry is configured to control a second set of lock indicators for the set of registers.

4 . The apparatus of claim 1 , wherein the lock circuitry is further configured to, in response to the reset event:
clear entries in the operand cache that are not indicated as being last-use.

5 . The apparatus of claim 1 , wherein indications of last-use for one or more operand cache entries are based on last-use hint information from a compiler.

6 . The apparatus of claim 1 , wherein the lock circuitry is configured to maintain lock indicators at single-instruction multiple-data (SIMD) granularity for threads in a SIMD group.

7 . The apparatus of claim 1 , further comprising:
decode circuitry configured to decode instructions for execution and indicate the registers utilized by instructions of the first thread.

8 . The apparatus of claim 1 , wherein the lock circuitry is configured to switch between sets of lock indicators for the set of registers in response to the reset event.

9 . The apparatus of claim 1 , wherein the processor pipeline circuitry is configured to pipeline, at least through a schedule pipeline stage, information that identifies a set of lock indicators corresponding to a given operation.

10 . The apparatus of claim 9 , wherein the processor pipeline circuitry is configured to perform a fence operation in response to the reset event such that all operations that use the first set of lock indicators reach a pipeline stage before any operations that use a second set of lock indicators proceed past the pipeline stage.

11 . The apparatus of claim 1 , wherein the reset event corresponds to a threshold number of registers in the set of registers being locked.

12 . The apparatus of claim 1 , wherein the reset event corresponds to a compiler hint.

13 . The apparatus of claim 1 , wherein the reset event corresponds to a threshold number of stall cycles of the first thread in a pipeline stage.

14 . A method, comprising:
storing, by a computing system in an operand cache, register operand data for operations performed by a processor pipeline of the computing system; controlling, by the computing system, a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated as being utilized by instructions of the first thread; preserving, by the computing system, register operand data in a data cache, including to prevent eviction of a given cache line from the data cache based on an asserted lock indicator for register data stored in the given cache line; and in response to a reset event, the computing system:
flushing operand data to the data cache from one or more entries of the operand cache indicated as being last-use; and
clear the first set of lock indicators.

15 . The method of claim 14 , further comprising, in response to the reset event:
asserting one or more lock indicators for the registers whose operand data was flushed from the one or more operand cache entries.

16 . The method of claim 15 , wherein the asserting includes controlling a second set of lock indicators for the set of registers.

17 . The method of claim 14 , further comprising, in response to the reset event:
clearing entries in the operand cache that are not indicated as being last-use.

18 . An apparatus, comprising:
processor pipeline circuitry configured to perform operations on register operand data; control circuitry configured to provide memory backing for register operand data in a memory hierarchy, wherein the memory hierarchy includes: a data cache at a first cache level; scoreboard circuitry configured to track which architectural registers are stored at the first cache level; and lock circuitry configured to:
initiate a map request to confirm whether operand data for registers that are indicated as being utilized by instructions of a first thread are stored at the first cache level;
in response to the scoreboard circuitry confirming that one or more registers utilized by instructions of the first thread are stored at the first cache level, control a first set of lock indicators for a set of registers for the first thread, including to assert one or more lock indicators corresponding to the confirmed one or more registers; and
preserve register operand data in the data cache, including to prevent eviction of a given cache line from the data cache based on an asserted lock indicator for a register stored in the given cache line.

19 . The apparatus of claim 18 , wherein the lock circuitry is further configured to:
clear the first set of lock indicators in response to a reset event.

20 . The apparatus of claim 18 , further comprising:
control circuitry configured to, in response to the scoreboard circuitry confirming that a register utilized by an instruction of the first thread is not stored at the first cache level, initiate a fetch operation from the memory hierarchy to the first cache level.

Assignees

• Apple Inc

Inventors

• Redshaw Jonathan M
• Yeung Winnie W
• Goodman Benjiman L
• Li David K
• Zhang Zelin
• Foo Yoong Chert

Classifications

• G06F9/382

  Pipelined decoding, e.g. using predecoding · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F2212/454

  Vector or matrix data · CPC title

• G06F2212/455

  Image or video data · CPC title