Tiled processor communication fabric

Patent metadata

Field	Value
Publication number	US-11941742-B2
Application number	US-202217808392-A
Country	US
Kind code	B2
Filing date	Jun 23, 2022
Priority date	Jun 23, 2022
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

Techniques are disclosed relating to processor communications fabrics. In some embodiments, a processor includes multiple client circuitry and fabric circuitry that includes at least first and second instances of a tile. The tile may include: client inputs configured to interface with client circuits, tile inputs configured to interface with one or more other tile instances, and communication resources assignable to the client inputs and tile inputs. The communications resources may include: multiple internal links, client outputs configured to interface with client circuits, and tile outputs configured to interface with one or more other tile instances. Control circuitry may, in a given cycle, assign communication resources of a given tile instance to at least a portion of the client inputs and tile inputs for a next cycle, based on priority information. The control circuitry may update priority information based on assignment results over multiple cycles.

First claim

What is claimed is:

1. An apparatus, comprising a processor that includes:
multiple client circuits;
fabric circuitry that includes at least first and second instances of a tile, wherein the tile includes:
client inputs configured to interface with client circuits;
tile inputs configured to interface with one or more other tile instances; and
communication resources assignable to the client inputs and tile inputs, wherein the communication resources include:
multiple internal links;
client outputs configured to interface with client circuits; and
tile outputs configured to interface with one or more other tile instances;

control circuitry configured to:
in a given cycle, assign communication resources of a given tile instance to at least a portion of the client inputs and tile inputs for a next cycle based on priority information for the tile instance's inputs; and
update priority information for a given tile instance of the fabric circuitry based on assignment results over multiple cycles.

2. The apparatus of claim 1 , wherein to assign communication resources of a given tile instance, the control circuitry is configured to:
determine priority information for the tile instance's inputs;
at least partially in parallel for multiple communication resources and multiple inputs, determine a number of inputs having a higher priority than a given input and that request the same resource;
determine, for a given resource, a number of inputs that the resource is able to service in the given cycle; and
assign communication resources to inputs for the given cycle based on the determinations of the numbers of inputs.

3. The apparatus of claim 1 , wherein the communication resources include:
dedicated resources for one or more non-stallable virtual channels; and
arbitrated resources for stallable virtual channels.

4. The apparatus of claim 3 , wherein the control circuitry is configured to assign a set of highest-priority indications to non-stallable virtual channel inputs.

5. The apparatus of claim 1 , wherein to update the priority information for a given tile instance based on assignment results over multiple cycles, the control circuitry is configured to:
categorize inputs to the tile instance based on whether they received all or a portion of requested resources over the multiple cycles; and
update priorities for inputs to the tile instance based on the categorization.

6. The apparatus of claim 5 ,
wherein the categories of inputs include:
a winner category for inputs whose most recent valid request was fully allocated all requested resources;
a partial winner category for inputs whose most recent valid request was not fully allocated all requested resources within the multiple cycles, for which a previous request was fully allocated all requested resources within the multiple cycles;
a loser category for which no valid requests were fully allocated requested resources within the multiple cycles; and
an invalid category for inputs for which no valid requests were received within the multiple cycles.

7. The apparatus of claim 6 , wherein to update the priorities, the control circuitry is configured to prioritize according to the following order from highest to lowest priority:
loser inputs;
invalid inputs;
partial-winner inputs; then
winner inputs.

8. The apparatus of claim 7 , wherein to update the priorities, the control circuitry is further configured to reverse priority ordering among the partial-winner inputs and reverse priority ordering among the winner inputs.

9. The apparatus of claim 1 , wherein the first tile instance includes multiple slices and the multiple internal links are links between slices.

10. The apparatus of claim 9 , wherein the slices are arranged in a chain topology and wherein the first tile instance includes a crossbar at one or both ends of the chain of slices, wherein the crossbar is connected to buffers configured to store:
data for the tile outputs; and
data from the tile inputs.

11. The apparatus of claim 1 , wherein the first and second instances of the tile include different numbers of inputs and different amounts of communication resources.

12. The apparatus of claim 1 , wherein the fabric circuitry includes:
a chain of tile instances that includes the first and second instances of the tile, wherein tile instances that are adjacent in the chain are connected via at least a portion of a given tile instance's tile inputs and tile outputs.

13. The apparatus of claim 1 , wherein the apparatus is a computing device that further includes:
a display; and
network interface circuitry.

14. The apparatus of claim 1 , wherein the processor includes:
a plurality of single-instruction multiple-data pipelines configured to execute instructions; and
fixed-function circuitry configured to control the single-instruction multiple-data pipelines perform operations for at least one of the following types of programs:
graphics shader programs; and
machine learning programs.

15. A method, comprising:
a computing system assigning communication resources of tiled fabric circuitry for a given cycle, wherein the fabric includes at least first and second instances of a tile, wherein the tile includes:
client inputs configured to interface with client circuits of the computing system;
tile inputs configured to interface with one or more other tile instances; and
communication resources assignable to the client inputs and tile inputs, wherein the communication resources include:
multiple internal links;
client outputs configured to interface with client circuits; and
tile outputs configured to interface with one or more other tile instances;

wherein the assigning includes assigning communications resources of a given tile instance to at least a portion of the client inputs and tile inputs for a next cycle based on priority information for the tile instance's inputs; and
updating, by the computing system, priority information for a given tile instance of the fabric circuitry based on assignment results over multiple cycles.

16. The method of claim 15 , wherein the assigning includes:
determining priority information for the tile instance's inputs;
at least partially in parallel for multiple communication resources and multiple inputs, determining a number of inputs having a higher priority than a given input and that request the same resource;
determining, for a given resource, a number of inputs that the resource is able to service in the given cycle; and
assigning communication resources to inputs for the given cycle based on the determinations of the numbers of inputs.

17. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:
multiple client circuits;
fabric circuitry that includes at least first and second instances of a tile, wherein the tile includes:
client inputs configured to interface with client circuits;
tile inputs configured to interface with one or more other tile instances; and
communication resources assignable to the client inputs and tile inputs, wherein the communication resources include:
multiple internal links;
client outputs configured to interface with client circuits; and
tile outputs configured to interface with one or

Assignees

• Apple Inc

Inventors

• Smith Adam J
• Tota Sergio V
• Martin Christopher G
• Foo Yoong Chert
• Potter Terence M
• Batley Max J

Classifications

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title