Preemption techniques for memory-backed registers

Patent metadata

Field	Value
Publication number	US-12353330-B2
Application number	US-202218054388-A
Country	US
Kind code	B2
Filing date	Nov 10, 2022
Priority date	Sep 19, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Techniques are disclosed relating to thread preemption in the context of memory-backed registers. In some embodiments, a memory hierarchy includes one or more cache levels and one or more memory circuits. Execution circuitry may operate on operands in architectural registers to execute instructions of threads, where data for the architectural registers is stored and backed by the memory hierarchy. Control circuitry may, in response to a context switch indication for a given thread: flush and invalidate a set of architectural register data from a first cache level and store memory page information (e.g., a page catalog base address) associated with the set of architectural register data.

First claim

What is claimed is:

1. A method, comprising:
operating, by a computing device, on operands in architectural registers to execute instructions of threads, wherein data for the architectural registers is stored and backed by a memory hierarchy that includes one or more cache levels and one or more memory circuits;
in response to a context switch indication for a given thread, the computing device:
identifying a set of cache lines at a first cache level that stored, prior to the context switch indication, a set of architectural register data for the given thread;
flushing and invalidating the identified set of cache lines; and

storing memory page information that indicates backing memory pages of the set of cache lines that were flushed and invalidated.

2. The method of claim 1 , wherein the memory page information includes a page catalog base address.

3. The method of claim 1 , further comprising:
allocating, by the computing device, one or more pages for the set of architectural register data; and
restoring, by the computing device, the one or more pages based on the stored memory page information in response to restoration of the thread.

4. The method of claim 3 , further comprising:
retrieving and caching, by the computing device, one or more pages in a page table cache based on the stored memory page information.

5. The method of claim 1 , further comprising:
accessing the first cache level using addresses in a private memory space for the given thread; and
using address information in a second memory space to store the memory page information.

6. The method of claim 5 , wherein the private memory space for the thread that is addressed at least in part based on hardware identifier information, the method further comprising:
storing, by the computing device, virtual hardware identifier information for the thread in response to the context switch indication and restoring the virtual hardware identifier information for the thread in response to restoration of the thread.

7. The method of claim 1 , further comprising:
storing, by the computing device, operand data in an operand cache at a level that is nearer, in the memory hierarchy, to execution circuitry than the first cache level.

8. A non-transitory computer-readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit, wherein the design information is usable by a semiconductor fabrication system to produce the circuit according to the design, including:
a memory hierarchy that includes one or more cache levels and one or more memory circuits;
execution circuitry configured to operate on operands in architectural registers to execute instructions of threads, wherein data for the architectural registers is stored and backed by the memory hierarchy under hardware control; and
control circuitry configured to, in response to a context switch indication for a given thread:
identify a set of cache lines at a first cache level that stored, prior to the context switch indication, a set of architectural register data for the given thread;
flush and invalidate the identified set of cache lines; and

store memory page information that indicates backing memory pages of the set of cache lines that were flushed and invalidated.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the memory page information includes a page catalog base address.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the circuit further includes:
memory allocator circuitry configured to:
allocate one or more pages for the set of architectural register data; and
restore the one or more pages based on the stored memory page information in response to restoration of the thread; and

memory management unit circuitry configured to retrieve and cache one or more pages based on the stored memory page information.

11. The non-transitory computer-readable storage medium of claim 8 , wherein the control circuitry is configured to:
access the first cache level using addresses in a private memory space for the given thread; and
use address information in a second memory space to store the memory page information.

12. An apparatus, comprising:
a memory hierarchy that includes one or more cache levels and one or more memory circuits;
execution circuitry configured to operate on operands in architectural registers to execute instructions of threads, wherein data for the architectural registers is stored and backed by the memory hierarchy under hardware control; and
control circuitry configured to, in response to a context switch indication for a given thread:
identify a set of cache lines at a first cache level that stored, prior to the context switch indication, a set of architectural register data for the given thread;
flush and invalidate the identified set of cache lines; and
store memory page information that indicates backing memory pages of the set of cache lines that were flushed and invalidated.

13. The apparatus of claim 12 , wherein the memory page information includes a page catalog base address.

14. The apparatus of claim 12 , further comprising:
memory allocator circuitry configured to:
allocate one or more pages for the set of architectural register data; and
restore the one or more pages based on the stored memory page information in response to restoration of the thread.

15. The apparatus of claim 14 , further comprising:
memory management unit circuitry configured to retrieve and cache one or more pages based on the stored memory page information.

16. The apparatus of claim 12 , wherein the control circuitry is configured to:
access the first cache level using addresses in a private memory space for the given thread; and
use address information in a second memory space to store the memory page information.

17. The apparatus of claim 16 , wherein:
the private memory space is addressed at least in part based on hardware identifier information; and
the control circuitry is configured to store virtual hardware identifier information for the thread in response to the context switch indication and restore the virtual hardware identifier information for the thread in response to restoration of the thread.

18. The apparatus of claim 12 , further comprising:
an operand cache configured to store operand data at a level that is nearer the execution circuitry in the memory hierarchy than the first cache level.

19. The apparatus of claim 12 , wherein the apparatus is a computing device that further includes:
a graphics processor that includes the execution circuitry and the control circuitry;
a central processing unit;
a display; and
network interface circuitry.

20. The apparatus of claim 12 , wherein the apparatus includes:
a plurality of single-instruction multiple-data pipelines configured to execute instructions; and
fixed-function circuitry configured to control the single-instruction multiple-data pipelines to perform operations for at least one of the following types of programs:
graphics shader programs; and
machine learning programs.

Assignees

• Apple Inc

Inventors

• Goodman Benjiman L
• Foo Yoong Chert
• Mann Karl D
• Potter Terence M
• Liljeros Frank W
• Brady Jeffrey T

Classifications

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F2212/6042

  Allocation of cache space to multiple users or processors · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F12/0857

  by multiple requestors · CPC title