Core isolation for errors
US-2025390371-A1 · Dec 25, 2025 · US
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Evers Marius patents
Evers Marius is listed as an inventor on 50 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Evers Marius |
| Total patents | 50 |
| First publication | Jan 22, 2015 |
| Latest publication | Dec 25, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Protection against branch target buffer poisoning by a management layer
US-12443702-B1 · Oct 14, 2025 · US
Storing incidental branch predictions to reduce latency of misprediction recovery
US-12204908-B2 · Jan 21, 2025 · US
Processor-guided execution of offloaded instructions using fixed function operations
US-12153926-B2 · Nov 26, 2024 · US
Merged branch target buffer entries
US-12153927-B2 · Nov 26, 2024 · US
Processor-guided execution of offloaded instructions using fixed function operations
US-2024126552-A1 · Apr 18, 2024 · US
Processor-guided execution of offloaded instructions using fixed function operations
US-11868777-B2 · Jan 9, 2024 · US
Protection against branch target buffer poisoning by a management layer
US-11797665-B1 · Oct 24, 2023 · US
Context partitioning of branch prediction structures
US-11734011-B1 · Aug 22, 2023 · US
Retaining cache entries of a processor core during a powered-down state
US-11704248-B2 · Jul 18, 2023 · US
Recent patents
Latest publications not already listed above.
Instruction cache prefetch throttle
US-11620224-B2 · Apr 4, 2023 · US
Selectively performing ahead branch prediction based on types of branch instructions
US-11416256-B2 · Aug 16, 2022 · US
Processor-guided execution of offloaded instructions using fixed function operations
US-2022188117-A1 · Jun 16, 2022 · US
Scheduler queue assignment burst mode
US-11334384-B2 · May 17, 2022 · US
Using loop exit prediction to accelerate or suppress loop mode of a processor
US-11256505-B2 · Feb 22, 2022 · US
Merged branch target buffer entries
US-2021373896-A1 · Dec 2, 2021 · US
Branch target buffer with early return prediction
US-11055098-B2 · Jul 6, 2021 · US
Tracking stores and loads by bypassing load store units
US-11048506-B2 · Jun 29, 2021 · US
Using loop exit prediction to accelerate or suppress loop mode of a processor
US-2021191722-A1 · Jun 24, 2021 · US
Instruction cache prefetch throttle
US-2021173783-A1 · Jun 10, 2021 · US
Scheduler queue assignment burst mode
US-2021173702-A1 · Jun 10, 2021 · US
Taint protection during speculative execution
US-10956157-B1 · Mar 23, 2021 · US
Retaining cache entries of a processor core during a powered-down state
US-10956332-B2 · Mar 23, 2021 · US
Processor with accelerated lock instruction operation
US-10949201-B2 · Mar 16, 2021 · US
Retaining cache entries of a processor core during a powered-down state
US-2021056031-A1 · Feb 25, 2021 · US
Selective use of taint protection during speculative execution
US-10929141-B1 · Feb 23, 2021 · US
Using loop exit prediction to accelerate or suppress loop mode of a processor
US-10915322-B2 · Feb 9, 2021 · US
Selectively performing ahead branch prediction based on types of branch instructions
US-2021034370-A1 · Feb 4, 2021 · US
Low latency synchronization for operation cache and instruction cache fetching and decoding instructions
US-10896044-B2 · Jan 19, 2021 · US
Using return address predictor to speed up control stack return address verification
US-10768937-B2 · Sep 8, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Advanced Micro Devices Inc | 50 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/3844 | 19 |
| G06F9/3806 | 17 |
| Y02D10/00 | 13 |
| G06F9/3861 | 12 |
| G06F9/3834 | 11 |