Retaining cache entries of a processor core during a powered-down state

Patent metadata

Field	Value
Publication number	US-11704248-B2
Application number	US-202017091993-A
Country	US
Kind code	B2
Filing date	Nov 6, 2020
Priority date	Nov 1, 2017
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

First claim

What is claimed is:

1. A method comprising:
based on one or more invalidation requests received while a processor core associated with a first cache is in a powered-down state and in response to the processor core associated with the first cache initiating exit from the powered-down state:
selectively repopulating, the first cache with entries that were not invalidated, wherein selectively repopulating includes:
using information, stored in a retention region, representing a set of entries of the first cache and indicating at least one entry of the set of entries was invalidated while the processor core was in the powered-down state.

2. The method of claim 1 , further comprising:
in response to powering down the processor core, storing the information representing the set of entries of the first cache in the retention region of a processing system that receives a retention voltage while the processor core is in the powered-down state.

3. The method of claim 1 , wherein the retention region comprises at least one of a second cache that is inclusive of the first cache, an external memory that stores information that is cached in the first cache, and a portion of the first cache that receives a retention voltage while the processor core is in the powered-down state.

4. The method of claim 1 , wherein the first cache is a translation lookaside buffer (TLB) that caches virtual-to-physical address translations for the processor core.

5. The method of claim 4 , wherein storing the information representing the set of entries of the TLB comprises storing the set of entries in the retention region, and wherein restoring the set of entries of the TLB comprises providing the set of entries stored in the retention region to the TLB.

6. The method of claim 4 , wherein:
storing the information representing the set of entries of the TLB comprises storing, in the retention region, virtual addresses of the set of entries in the TLB; and
restoring the set of entries of the TLB comprises prefetching the virtual addresses to initiate page table walks that populate the set of entries in the TLB.

7. The method of claim 4 , further comprising:
storing the information indicating the at least one entry of the set of entries has been invalidated while the processor core was in the powered-down state in a queue in response to receiving an invalidation request that invalidates the at least one entry while the processor core is in the powered-down state.

8. The method of claim 7 , further comprising:
invalidating the TLB in response to the queue overflowing with the one or more invalidation requests.

9. The method of claim 1 , further comprising:
storing, in the retention region, the information indicating the at least one entry of the set of entries of the first cache has been invalidated while the processor core is in the powered-down state;
implementing, at the retention region, a probe queue to store cache probes that are received while the processor core is in the powered-down state; and
selectively repopulating the first cache using the cache probes stored in the probe queue.

10. The method of claim 9 , wherein:
the first cache is a lower-level cache in a cache hierarchy that includes a second cache that is inclusive of the first cache; and
storing the information representing the set of entries in the first cache comprises at least one of rinsing the first cache to write modified values of the set of entries to the second cache or an external memory and flushing the first cache to write all values of the set of entries to the second cache or the external memory.

11. The method of claim 10 , wherein:
storing the information representing the set of entries in the first cache comprises storing physical addresses of the set of entries in shadow tags associated with the set of entries in the second cache or the external memory;
storing the information indicating the at least one entry of the set of entries of the first cache has been invalidated while the processor core is in the powered-down state comprises storing the information in the shadow tags; and
restoring the set of entries in the first cache comprises prefetching valid entries in the first cache based on the physical addresses of the set of entries and the information indicating the at least one entry of the set of entries of the first cache has been invalidated while the processor core is in the powered-down state in the shadow tags.

12. An apparatus, comprising:
a processor core configured to access information from a first cache; and
a retention region that receives a retention voltage while the processor core is in a powered-down state; wherein:
based on one or more one or more invalidation requests received when the processor core is in the powered-down state and in response to the processor core initiating exit from the powered-down state:
the first cache is selectively repopulated with entries of a set of entries that were not invalidated; and
the first cache is selectively repopulated using information, stored in the retention region, representing the set of entries of the first cache and indicating at least one entry of the set of entries of the first cache has been invalidated while the processor core was in the powered-down state.

13. The apparatus of claim 12 , wherein the retention region comprises at least one of a second cache that is inclusive of the first cache, an external memory that stores information that is cached in the first cache, and a portion of the first cache that receives the retention voltage while the processor core is in the powered-down state.

14. The apparatus of claim 12 , wherein the first cache is a translation lookaside buffer (TLB) that caches virtual-to-physical address translations for the processor core.

15. The apparatus of claim 14 , further comprising:
a queue configured to store the information indicating the at least one entry of the first cache has been invalidated while the processor core is in the powered-down state in response to receiving an invalidation request that invalidates the at least one entry while the processor core is in the powered-down state.

16. The apparatus of claim 12 , wherein the first cache is a lower-level cache in a cache hierarchy that includes a second cache that is inclusive of the first cache.

17. A method comprising:
selectively restoring, based one or more invalidation requests received while a processor core was in a powered-down state, entries of a cache that were not invalidated, the selectively restoring further based on stored information in a retention region of a processing system representative of the entries of the cache and at least one cache probe stored in a probe queue.

18. The method of claim 17 , further comprising:
storing the information representing the entries of the cache in the retention region in response to a processor core of the processing system initiating entry into a powered-down state, wherein the retention region receives a retention voltage concurrently with the processor core being in the powered-down state; and
implementing the probe queue at the retention region to store cache probes that are received while the processor core is powered down.

19. The method of claim 17 , wherein selectively restoring the entries comprises storing information indicating an invalidated entry in response to receiving an invalidation request invalidating an entry of the cache while the processor core is in the powered-down state and restoring the cache based on valid entries.

Assignees

• Advanced Micro Devices Inc

Inventors

• Walker William L
• Golden Michael L
• Evers Marius

Classifications

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title