Instruction cache prefetch throttle

Patent metadata

Field	Value
Publication number	US-11620224-B2
Application number	US-201916709831-A
Country	US
Kind code	B2
Filing date	Dec 10, 2019
Priority date	Dec 10, 2019
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

Techniques for controlling prefetching of instructions into an instruction cache are provided. The techniques include tracking either or both of branch target buffer misses and instruction cache misses, modifying a throttle toggle based on the tracking, and adjusting prefetch activity based on the throttle toggle.

First claim

What is claimed is:

1. A method for controlling prefetching of instructions into an instruction cache, the method comprising:
tracking a number of misses in a branch target buffer and the instruction cache, wherein the number of misses indicates a number of consecutive branch target buffer and instruction cache misses;
modifying a throttle toggle based on the tracking; and
adjusting prefetch activity for the instruction cache based on the throttle toggle.

2. The method of claim 1 , further comprising:
modifying a throttling degree based on the tracking, wherein the throttling degree indicates a degree to which throttling occurs,
wherein adjusting the prefetch activity is also performed based on the throttling degree.

3. The method of claim 1 , wherein:
the tracking comprises detecting that the number of consecutive branch target buffer and instruction cache misses is above a first threshold, and, in response, the modifying comprises setting the throttle toggle to indicate that instruction cache prefetching is to be throttled.

4. The method of claim 1 , wherein:
the tracking comprises detecting that the number of consecutive branch target buffer and instruction cache misses is not above a first threshold, and, in response, the modifying comprises setting the throttle toggle to indicate that instruction cache prefetching is not to be throttled.

5. The method of claim 1 , wherein:
the tracking comprises detecting that the number of consecutive branch target buffer and instruction cache misses is above a first threshold and that a number of outstanding branch target buffer and instruction cache misses is above a second threshold, and, in response, the modifying comprises setting the throttle toggle to indicate that instruction cache prefetching is to be throttled.

6. The method of claim 1 , wherein the tracking comprises:
not determining the number of misses in the instruction cache.

7. The method of claim 1 , wherein the tracking comprises:
not determining the number of misses in the branch target buffer.

8. The method of claim 2 , wherein the throttling degree indicates one of a number of instructions that are prefetched or a number of caches into which prefetching of instructions occurs.

9. An instruction fetching system for controlling prefetching of instructions into an instruction cache, the instruction fetching system comprising:
a branch target buffer; and
a miss tracker configured to:
track a number of misses in a branch target buffer and the instruction cache, wherein the number of misses indicates a number of consecutive branch target buffer and instruction cache misses;
modify a throttle toggle based on the tracking; and
adjust prefetch activity for the instruction cache based on the throttle toggle.

10. The instruction fetching system of claim 9 , wherein the miss tracker is further configured to:
modify a throttling degree based on the tracking, wherein the throttling degree indicates a degree to which throttling occurs,
wherein adjusting the prefetch activity is also performed based on the throttling degree.

11. The instruction fetching system of claim 9 , wherein the miss tracker is further configured to:
detect that the number of consecutive branch target buffer and instruction cache misses is above a first threshold, and, in response, the modifying comprises setting the throttle toggle to indicate that instruction cache prefetching is to be throttled.

12. The instruction fetching system of claim 9 , wherein the miss tracker is further configured to:
detect that the number of consecutive branch target buffer and instruction cache misses is not above a first threshold, and, in response, the modifying comprises setting the throttle toggle to indicate that instruction cache prefetching is not to be throttled.

13. The instruction fetching system of claim 9 , wherein the miss tracker is further configured to:
detect that the number of consecutive branch target buffer and instruction cache misses is above a first threshold and that a number of outstanding branch target buffer and instruction cache misses is above a second threshold, and, in response, the modifying comprises setting the throttle toggle to indicate that instruction cache prefetching is to be throttled.

14. The instruction fetching system of claim 9 , wherein:
the tracking comprises not determining the number of misses in the instruction cache.

15. The instruction fetching system of claim 9 , wherein:
the tracking comprises not determining the number of misses in the branch target buffer.

16. The instruction fetching system of claim 10 , wherein the throttling degree indicates one of a number of instructions that are prefetched or a number of caches into which prefetching of instructions occurs.

17. A processor comprising:
an instruction cache;
a branch target buffer; and
a miss tracker configured to:
track a number of misses in the branch target buffer and the instruction cache, wherein the number of misses indicates a number of consecutive branch target buffer and instruction cache misses;
modify a throttle toggle based on the tracking; and
adjust prefetch activity for the instruction cache based on the throttle toggle.

18. The processor of claim 17 , wherein the miss tracker is further configured to:
modify a throttling degree based on the tracking, wherein the throttling degree indicates a degree to which throttling occurs,
wherein adjusting the prefetch activity is also performed based on the throttling degree.

19. The processor of claim 17 , wherein the miss tracker is further configured to:
detect that the number of consecutive branch target buffer and instruction cache misses is above a first threshold, and, in response, the modifying comprises setting the throttle toggle to indicate that instruction cache prefetching is to be throttled.

20. The processor of claim 17 , wherein the miss tracker is further configured to:
detect that the number of consecutive branch target buffer and instruction cache misses is not above a first threshold, and, in response, the modifying comprises setting the throttle toggle to indicate that instruction cache prefetching is not to be throttled.

21. The processor of claim 17 , wherein the miss tracker is further configured to:
detect that the number of consecutive branch target buffer and instruction cache misses is above a first threshold and that a number of outstanding branch target buffer and instruction cache misses is above a second threshold, and, in response, the modifying comprises setting the throttle toggle to indicate that instruction cache prefetching is to be throttled.

22. The processor of claim 17 , wherein:
the tracking comprises not determining the number of misses in the instruction cache.

23. The processor of claim 17 , wherein:
the tracking comprises not determining the number of misses in the branch target buffer.

24. The processor of claim 18 , wherein the throttling degree indicates one of a number of instructions that are prefetched or a number of caches into which prefetching of instructions occurs.

Assignees

• Advanced Micro Devices Inc

Inventors

• Thyagarajan Aparna
• Venkatachar Ashok Tirupathy
• Evers Marius
• Wong Angelo
• Jones William E

Classifications

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F2212/1021

  Hit rate improvement · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F9/3808

  for instruction reuse, e.g. trace cache, branch target cache · CPC title