Using loop exit prediction to accelerate or suppress loop mode of a processor

Patent metadata

Field	Value
Publication number	US-10915322-B2
Application number	US-201816134440-A
Country	US
Kind code	B2
Filing date	Sep 18, 2018
Priority date	Sep 18, 2018
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

First claim

What is claimed is:

1. A method comprising:
in a processor, predicting a number of loop iterations expected to be executed for a loop associated with a set of loop instructions; and
in response to the predicted number of loop iterations exceeding a first loop iteration threshold, executing the set of loop instructions in a loop mode, including:
placing at least one component of an instruction pipeline of the processor in a low-power mode; and
executing the set of loop instructions from a loop buffer.

2. The method of claim 1 , further comprising:
in response to the predicted number of loop iterations being less than a second loop iteration threshold, delaying entry into the loop mode until the threshold number of loop iterations has been executed.

3. The method of claim 2 , further comprising:
in response to the predicted number of loop iterations being greater than the second loop iteration threshold, entering the loop mode before the threshold number of loop iterations has been executed.

4. The method of claim 1 , wherein placing the at least one component of the instruction pipeline in the low-power mode includes placing a loop exit predictor of the processor in the low-power mode.

5. The method of claim 1 , further comprising:
after placing the at least one component of the instruction pipeline in the low-power mode, updating, by a loop exit predictor, the predicted number of loop iterations associated with the set of loop instructions; and
determining a timing of restoring power to the at least one component of the instruction pipeline in the low-power mode based on the updated number of loop iterations.

6. The method of claim 1 , further comprising:
prior to predicting the number of loop iterations, identifying instructions as the set of loop instructions by matching a characteristic of a loop instruction to an identifier in a set of stored loop identifiers.

7. The method of claim 1 , wherein the placing of the at least one component of the instruction pipeline in the low-power mode is performed prior to executing an instruction of the set of loop instructions.

8. The method of claim 1 , further comprising:
predicting an exit for the set of loop instructions during the loop mode.

9. A method comprising:
in a processor, in response to predicting a number of loop iterations expected to be executed for a loop associated with a set of loop instructions:
storing the set of loop instructions in a loop buffer;
placing a component of an instruction pipeline of the processor in a low-power mode;
executing the set of loop instructions from the loop buffer;
predicting a loop exit by a loop exit predictor of the processor; and
restoring power to the component placed in the low-power mode based on the predicted loop exit.

10. The method of claim 9 , further comprising:
comparing the predicted number of loop iterations with a first loop iteration threshold prior to powering down the component of the instruction pipeline.

11. The method of claim 9 , wherein the component of the instruction pipeline is placed in the low-power mode prior to executing the set of loop instructions from the loop buffer.

12. The method of claim 9 , wherein powering down the component of the instruction pipeline of the processor includes powering down a loop exit predictor of the processor.

13. A processor comprising:
an instruction cache having a set of loop instructions for the processor;
a loop buffer configured to store the set of loop instructions;
a loop exit predictor configured to predict a number of loop iterations expected to be executed for a loop associated with the set of loop instructions; and
wherein the processor is configured to:
in response to the predicted number of loop iterations exceeding a first loop iteration threshold, execute the set of loop instructions in a loop mode, including to:
place at least one component of an instruction pipeline of the processor in a low-power mode; and
execute the set of loop instructions from the loop buffer; and

in response to the predicted number of loop iterations being less than or equal to the first loop iteration threshold, execute the set of loop instructions in a non-loop mode, including to:
maintain the at least one component of the instruction pipeline in an active state; and
execute the set of loop instructions fetched from the instruction cache by an instruction fetch unit of the instruction pipeline.

14. The processor of claim 13 , further comprising:
a decoder for decoding the loop instructions into micro-operations for execution by a functional unit of the processor, and wherein the instruction fetch unit is configured to provide the loop instructions to the decoder from the instruction cache.

15. The processor of claim 14 , wherein the instruction fetch unit is configured to provide loop instructions to the loop exit predictor.

16. The processor of claim 13 , wherein the at least one component of the instruction pipeline placed in the low-power mode is an instruction fetch component of the processor.

17. The processor of claim 13 , wherein the at least one component of the instruction pipeline placed in the low-power mode is the loop exit predictor.

18. The processor of claim 13 , wherein the loop exit predictor is further configured to:
after placing the at least one component of the instruction pipeline in the low-power mode, update the number of loop iterations associated with the set of loop instructions; and
wherein a timing of restoring power to the at least one component of the instruction pipeline placed in the low-power mode is based on the updated number of loop iterations.

19. The processor of claim 13 , further comprising:
a buffer of stored loop identifiers; and
wherein the loop exit predictor is further configured to:
match a characteristic of the set of loop instructions to an identifier in the buffer of stored loop identifiers.

20. The processor of claim 13 , wherein placing the at least one component of the instruction pipeline in the low-power mode is performed prior to executing any instruction associated with the set of loop instructions and after predicting the number of loop iterations associated with the set of loop-instructions.

Assignees

• Advanced Micro Devices Inc

Inventors

• Annamalai Arunachalam
• Evers Marius
• Thyagarajan Aparna
• Jarvis Anthony

Classifications

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/381

  Loop buffering · CPC title

• G06F9/30083

  Power or thermal control instructions · CPC title

• G06F9/30065 Primary

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title