Method, system, and apparatus for page sizing extension
US-2021374069-A1 · Dec 2, 2021 · US
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Espasa Roger patents
Espasa Roger is listed as an inventor on 31 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Espasa Roger |
| Total patents | 31 |
| First publication | Oct 8, 2015 |
| Latest publication | Dec 2, 2021 |
Notable patents
Publications ranked by popularity score, then publication date.
Bit shuffle processors, methods, systems, and instructions
US-2021132950-A1 · May 6, 2021 · US
Method, system, and apparatus for page sizing extension
US-2020242046-A1 · Jul 30, 2020 · US
Bit shuffle processors, methods, systems, and instructions
US-10713044-B2 · Jul 14, 2020 · US
Method and apparatus for performing a vector permute with an index and an immediate
US-2020097290-A1 · Mar 26, 2020 · US
Method, system, and apparatus for page sizing extension
US-10445244-B2 · Oct 15, 2019 · US
Method, system, and apparatus for page sizing extension
US-10445245-B2 · Oct 15, 2019 · US
Method and apparatus for performing a vector permute with an index and an immediate
US-10445092-B2 · Oct 15, 2019 · US
Method and apparatus for performing a vector bit gather
US-10296334-B2 · May 21, 2019 · US
Method and apparatus for performing a vector bit shuffle
US-10296489-B2 · May 21, 2019 · US
Recent patents
Latest publications not already listed above.
Apparatus and method for vector horizontal logical instruction
US-2019138303-A1 · May 9, 2019 · US
Method, system, and apparatus for page sizing extension
US-9934155-B2 · Apr 3, 2018 · US
Three source operand floating-point addition instruction with operand negation bits and intermediate and final result rounding
US-2018032332-A1 · Feb 1, 2018 · US
Bit group interleave processors, methods, systems, and instructions
US-2017308383-A1 · Oct 26, 2017 · US
Three source operand floating-point addition instruction with operand negation bits and intermediate and final result rounding
US-9785433-B2 · Oct 10, 2017 · US
Bit shuffle processors, methods, systems, and instructions
US-2017286112-A1 · Oct 5, 2017 · US
Super multiply add (super madd) instruction
US-9733935-B2 · Aug 15, 2017 · US
Consecutive bit error detection and correction
US-9654143-B2 · May 16, 2017 · US
Indicating a length of an instruction of a variable length instruction set
US-9606931-B2 · Mar 28, 2017 · US
Apparatus and method for vector horizontal logical instruction
US-2016283242-A1 · Sep 29, 2016 · US
Technique for setting a vector mask
US-9436468-B2 · Sep 6, 2016 · US
Apparatus and method for fused multiply-multiply instructions
US-2016188327-A1 · Jun 30, 2016 · US
Method and apparatus for performing a vector bit shuffle
US-2016188532-A1 · Jun 30, 2016 · US
Method and apparatus for compressing a mask value
US-2016188333-A1 · Jun 30, 2016 · US
Method and apparatus for performing a vector bit gather
US-2016188335-A1 · Jun 30, 2016 · US
Apparatus and method for fused add-add instructions
US-2016188341-A1 · Jun 30, 2016 · US
Method and apparatus for performing a vector permute with an index and an immediate
US-2016188530-A1 · Jun 30, 2016 · US
Apparatus and method for vector broadcast and xorand logical instruction
US-2016179523-A1 · Jun 23, 2016 · US
Method, system, and apparatus for page sizing extension
US-9244855-B2 · Jan 26, 2016 · US
Consecutive bit error detection and correction
US-2015370636-A1 · Dec 24, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 28 |
| Espasa Roger | 7 |
| Sole Guillem | 3 |
| Fernandez Manel | 3 |
| Ould-Ahmed-Vall Elmoustapha | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30038 | 22 |
| G06F9/30036 | 22 |
| G06F9/30018 | 16 |
| G06F9/30032 | 12 |
| G06F12/1027 | 6 |