Consecutive bit error detection and correction

Patent metadata

Field	Value
Publication number	US-9654143-B2
Application number	US-201414308107-A
Country	US
Kind code	B2
Filing date	Jun 18, 2014
Priority date	Jun 18, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.

First claim

What is claimed is:

1. An apparatus comprising:
a storage structure in which to store 128 data bits of a plurality of 128-bit data values, four parity bits of a plurality of 4-bit party values, and eight error correction code (ECC) bits of a plurality of 8-bit ECC values, each parity value corresponding to one of the plurality of the data value, a first bit of each parity value corresponding to a first quadrant of the corresponding data value, wherein the first quadrant of the corresponding data value is interleaved with a second quadrant of the corresponding data value, wherein a second bit each parity value corresponds to the second quadrant of the corresponding data value, each ECC value corresponding to one of the plurality of data values, wherein a first ECC bit, a second ECC bit, and a third ECC bit of each ECC value are assigned to first data bit of the first quadrant, wherein the second ECC bit, the third ECC bit, and fourth ECC bit of each ECC value are assigned to the first data bit of the second quadrant, wherein the third ECC bit, the fourth ECC bit, and a fifth ECC bit of each ECC value are assigned to the first data bit of a third quadrant of the corresponding data value, and wherein the fourth ECC bit, the fifth ECC bit, and a sixth ECC bit of each ECC value are assigned to the first data bit of a fourth quadrant of the corresponding data value;
a parity checker to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value;
an ECC checker to be activated to generate a syndrome only if the parity checker detects the parity error; and
an error corrector to detect and, if the parity error corresponds to an error in a single data value bit or two physically consecutive data value bits, correct the error in the data value using the syndrome.

2. The apparatus of claim 1 , wherein at least two of the eight ECC bits are assigned to each of the 128 data bits such that any error in any two physically consecutive data bits is identifiable and correctable.

3. The apparatus of claim 2 , wherein each bit of each parity value is to cover a quadrant.

4. The apparatus of claim 3 , wherein each bit of each ECC value is to cover one of eight partially overlapping subsets of data bits in each quadrant according to a pattern.

5. The apparatus of claim 4 , wherein the pattern is shifted by one ECC bit per quadrant.

6. The apparatus of claim 1 , wherein the storage structure includes a first portion in which to store the plurality of data values and the plurality of parity values and a second portion in which to store the plurality of ECC values, the second portion physically separate from the first portion.

7. The apparatus of claim 1 , wherein the parity values and the ECC values provide error correction capability for errors in two consecutive bits.

8. The apparatus of claim 7 , wherein the parity values provide error detection capability for errors in four consecutive bits.

9. A method comprising:
detecting a parity error in a 128-bit data value using a 4-bit parity value corresponding to the data value, wherein a first bit of the parity value corresponds to a first quadrant of the data value, wherein the first quadrant of the data value is interleaved with a second quadrant of the data value, wherein a second bit of the parity value corresponds to the second quadrant of the data value, wherein each ECC value corresponds to one of the plurality of data values, wherein a first ECC bit, a second ECC bit, and a third ECC bit of each ECC value are assigned to first data bit of the first quadrant, wherein the second ECC bit, the third ECC bit, and a fourth ECC bit of each ECC value are assigned to the first data bit of the second quadrant, wherein the third ECC bit, the fourth ECC bit, and a fifth ECC bit of each ECC value are assigned to the first data bit of a third quadrant of the corresponding data value, and wherein the fourth ECC bit, the fifth ECC bit, and a sixth ECC bit of each ECC value are assigned to the first data bit of a fourth quadrant of the corresponding data value;
activating an ECC checker to generate an error correction code (ECC) syndrome using an ECC value corresponding to the data value only if the parity error is detected; and
detecting and, if the parity corresponds to an error in a single data value bit or two physically consecutive data value bits, correcting the error in the data value using the syndrome.

10. The method of claim 9 , wherein the portions are quadrants.

11. The method of claim 10 , the parity value and the ECC value provide error correction capability for errors in two consecutive bits, and the parity value provides error detection capability for errors in four consecutive bits.

12. The method of claim 9 , wherein at least two of the eight ECC bits are assigned to each of the 128 data bits such that any error in any two physically consecutive data bits is identifiable and correctable.

13. The method of claim 12 , wherein each of the eight ECC value is cover one of eight partially overlapping subsets of data bits in each quadrant according to a pattern.

14. The method of claim 13 , wherein the pattern is shifted by one ECC bit per quadrant.

15. A system comprising:
a system memory in which to store a plurality of 128-bit data values; and
a processor including:
a storage structure including 128 data bits in which to store a subset of the plurality of 128-bit data values, four parity in which to store a plurality of 4-bit parity values, and eight error correction code(ECC)bits in which to store a plurality of 8-bit ECC values, each parity value corresponding to one of the subset of the plurality of data values, a first bit of each parity value corresponding to a first quadrant of a corresponding data value, wherein the first quadrant of the corresponding data value is interleaved with a second quadrant of the corresponding data value, wherein a second bit of each parity value corresponds to the second quadrant of the corresponding data value, each ECC value corresponding to one of the plurality of data values, wherein a first ECC bit, a second ECC bit, and a third ECC bit of each ECC value are assigned to first data bit of the first quadrant, wherein the second ECC bit, the third ECC bit, and a fourth ECC bit of each ECC value are assigned to the first data bit of the second quadrant, wherein the third ECC bit, the fourth ECC bit, and a fifth ECC bit of each ECC value are assigned to the first data bit of a third quadrant of the corresponding data value, and wherein the fourth ECC bit, the fifth ECC bit, and a sixth ECC bit of each ECC value are assigned to the first data bit of a fourth quadrant of the corresponding data value;

a parity checker to detect a parity error in a data value stored in the storage structure using a parity value corresponding to the data value;
an ECC checker to be activated to generate a syndrome only if the parity checker detects the parity error; and
an error corrector to detect and, if the parity error corresponds to an error in a single data value bit or two physically consecutive data value bits, correct the error in the data value using the syndrome.

Assignees

• Intel Corp

Inventors

• Sole Guillem
• Espasa Roger
• Iacobovici Sorin
• Hickmann Brian
• Wu Wei
• Fletcher Thomas

Classifications

• H03M13/09 Primary

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• H03M13/29

  combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes · CPC title

• H03M13/19

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• H03M13/17

  Burst error correction, e.g. error trapping, Fire codes · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title