Method, system, and apparatus for page sizing extension

Patent metadata

Field	Value
Publication number	US-9934155-B2
Application number	US-201213722485-A
Country	US
Kind code	B2
Filing date	Dec 20, 2012
Priority date	Dec 31, 2007
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. A processor, comprising:
a plurality of execution cores; and
a first translation lookaside buffer (TLB) coupled to the plurality of execution cores, the first TLB to store a first plurality of cached page table entries (PTEs) to translate virtual addresses to physical addresses of memory pages, each PTE having at least 64 bits and a same format;
a second translation lookaside buffer (TLB) coupled to the plurality of execution cores, the second TLB to store a second plurality of cached page table entries (PTEs), the second plurality of cached PTEs corresponding to memory pages having a different size than the first plurality of cached PTEs of the first TLB, to translate virtual addresses to physical addresses of memory pages, each PTE having at least 64 bits and the same format, the format includes:
a first single bit to indicate whether a corresponding memory page is a 4-kilobyte (KB) memory page or a larger size memory page, wherein a plurality of sequential 4 KB size physical memory pages having corresponding consecutive PTEs are to be combined into and treated as the larger size memory page, wherein the first bit is to indicate whether the corresponding memory page is either the 4 KB memory page or a 64 KB memory page or larger,
a second bit to indicate whether the corresponding memory page has been written,
a third bit to indicate whether the corresponding memory page has been accessed, and
a fourth bit to indicate whether the corresponding PTE is able to be used to perform address translation.

2. The processor of claim 1 , wherein the larger size memory page is one of a 64 KB page and a 1024 KB page.

3. The processor of claim 1 , wherein the larger size memory page is one of a 64 KB, 1024 KB, 2 megabyte (MB), and 4 MB memory page.

4. The processor of claim 1 , wherein the fourth bit is also to indicate whether the corresponding memory page has been loaded into a physical memory.

5. The processor of claim 1 , wherein responsive to a TLB miss, a size of the corresponding memory page is determined at least in part from a state of the first bit of a corresponding PTE at the time the corresponding PTE is cached into the first or second TLB.

6. A system comprising:
a physical memory to store memory pages including a portion of the memory pages for an operating system;
a plurality of execution cores; and
a first translation lookaside buffer (TLB) coupled to the plurality of execution cores, the first TLB to store a first plurality of cached page table entries (PTEs) to translate virtual addresses to physical addresses of the memory pages, each PTE having at least 64 bits and a same format;
a second translation lookaside buffer (TLB) coupled to the plurality of execution cores, the second TLB to store a second plurality of cached page table entries (PTEs), the second plurality of cached PTEs corresponding to memory pages having a different size than the first plurality of cached PTEs of the first TLB, to translate virtual addresses to physical addresses of memory pages, each PTE having at least 64 bits and the same format, the format includes:
a first single bit to indicate whether a corresponding memory page is a 4-kilobyte (KB) memory page or a larger size memory page, wherein a plurality of sequential 4 KB size memory pages can be combined into and treated as the larger size memory page, wherein the first bit is to indicate whether the corresponding memory page is either the 4 KB memory page or a 64 KB memory page or larger,
a second bit to indicate whether the corresponding memory page has been written,
a third bit to indicate whether the corresponding memory page has been accessed, and
a fourth bit to indicate whether the corresponding PTE is able to be used to perform address translation;
said operating system to initialize a memory page of the larger size by initializing a plurality of consecutive PTEs for a corresponding plurality of sequential 4 KB size physical memory pages such that the total memory is the same as the larger size memory page.

7. The system of claim 6 , wherein the fourth bit is also to indicate whether the corresponding memory page has been loaded into the physical memory.

8. The system of claim 6 , wherein said operating system is to initialize consecutive PTEs for sixteen sequential 4 KB size memory pages such that the total memory is the same as a 64 KB memory page.

9. The system of claim 8 , wherein corresponding fourth bits indicate that the sixteen sequential 4 KB size memory pages have been loaded into the physical memory.

10. The system of claim 6 , comprising: setting at least the first bit in each of the plurality of consecutive PTEs to indicate the larger size.

11. The system of claim 6 , wherein responsive to a TLB miss, a size of the corresponding memory page is determined at least in part from the first bit of a corresponding PTE at the time the corresponding PTE is cached into the first or second TLB.

12. A method comprising:
storing a plurality of page table entries (PTEs) in physical memory to translate virtual addresses to physical addresses of physical memory pages, each PTE having at least 64 bits and a same format and further including:
a first single bit to indicate whether a corresponding memory page is a 4-kilobyte (KB) memory page or a larger size memory page, wherein a plurality of sequential 4 KB size physical memory pages having corresponding consecutive PTEs can be combined into and treated as the larger size memory page, wherein the first bit is to indicate whether the corresponding memory page is either the 4 KB memory page or a 64 KB memory page, wherein the first single bit to dictate between a first or a second TLB to store the PTE,
a second bit to indicate whether the corresponding memory page has been written,
a third bit to indicate whether the corresponding memory page has been accessed, and
a fourth bit to indicate whether the corresponding PTE is able to be used to perform address translation;
initializing a memory page of the larger size by initializing a plurality of consecutive PTEs in physical memory for a corresponding plurality of sequential 4 KB size physical memory pages such that the total physical memory is the same as the larger size memory page; and
setting a respective first bit in each of said plurality of consecutive PTEs to indicate whether a respective corresponding memory page is to be treated as a 4-kilobyte (KB) memory page or as a larger size memory page for translating virtual addresses to physical addresses of the respective corresponding memory page.

13. The method of claim 12 , wherein the fourth bit is also to indicate whether the corresponding memory page has been loaded into the physical memory.

14. The method of claim 12 , wherein said initializing said plurality of consecutive PTEs in physical memory is for sixteen sequential 4 KB size physical memory pages such that the total physical memory for said sixteen sequential 4 KB size physical memory pages is the same as a 64 KB physical memory page.

Assignees

• Intel Corp

Inventors

• Grochowski Edward
• Gago Julio
• Gramunt Roger
• Espasa Roger
• Kassa Rolf

Classifications

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/6032

  Way prediction in set-associative cache · CPC title

• G06F12/145

  the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title

• G06F2212/652

  Page size control · CPC title

• G06F12/0864

  using pseudo-associative means, e.g. set-associative or hashing · CPC title