Three source operand floating-point addition instruction with operand negation bits and intermediate and final result rounding

Patent metadata

Field	Value
Publication number	US-9785433-B2
Application number	US-201514645836-A
Country	US
Kind code	B2
Filing date	Mar 12, 2015
Priority date	Mar 26, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A processor includes a decode unit to decode a three source floating point addition instruction indicating a first source operand having a first floating point data element, a second source operand having a second floating point data element, and a third source operand having a third floating point data element. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, stores a result in a destination operand indicated by the instruction. The result includes a result floating point data element that includes a first floating point rounded sum. The first floating point rounded sum represents an additive combination of a second floating point rounded sum and the third floating point data element. The second floating point rounded sum represents an additive combination of the first floating point data element and the second floating point data element.

First claim

What is claimed is:

1. A processor comprising:
a plurality of registers;
a decode unit to decode a three source floating point addition instruction, the three source floating point addition instruction to indicate a first source operand that is to have at least a first floating point data element, to indicate a second source operand that is to have at least a second floating point data element, and to indicate a third source operand that is to have at least a third floating point data element, wherein the decode unit is to decode the three source floating point addition instruction which is to have:
a first bit to specify whether all of one or more floating point data elements of the first source operand are to be negated;
a second bit to specify whether all of one or more floating point data elements of the second source operand are to be negated; and
a third bit to specify whether all of one or more floating point data elements of the third source operand are to be negated; and

an execution unit coupled with the plurality of registers and the decode unit, the execution unit, in response to the three source floating point addition instruction, to store a result in a destination operand that is to be indicated by the three source floating point addition instruction, the result to include at least a result floating point data element that is to correspond to the first, second, and third floating point data elements, the result floating point data element to include a first floating point rounded sum, the first floating point rounded sum to represent an additive combination of a second floating point rounded sum and the third floating point data element, the second floating point rounded sum to represent an additive combination of the first floating point data element and the second floating point data element.

2. The processor of claim 1 , wherein the first, second, and third bits comprise bits of an immediate of the three source floating point addition instruction.

3. A processor comprising:
a plurality of registers;
a decode unit to decode a three source floating point addition instruction, the three source floating point addition instruction to indicate a first source operand that is to have at least a first floating point data element, to indicate a second source operand that is to have at least a second floating point data element, and to indicate a third source operand that is to have at least a third floating point data element, wherein the decode unit is to decode the three source floating point addition instruction which is to specify whether all of one or more floating point data elements of the first source operand are to be negated, and wherein the decode unit is to decode the three source floating point addition instruction which is to specify whether all of one or more floating point data elements of the second source operand are to be negated; and
an execution unit coupled with the plurality of registers and the decode unit, the execution unit, in response to the three source floating point addition instruction, to store a result in a destination operand that is to be indicated by the three source floating point addition instruction, the result to include at least a result floating point data element that is to correspond to the first, second, and third floating point data elements, the result floating point data element to include a first floating point rounded sum, the first floating point rounded sum to represent an additive combination of a second floating point rounded sum and the third floating point data element, the second floating point rounded sum to represent an additive combination of the first floating point data element and the second floating point data element.

4. The processor of claim 3 , wherein the decode unit is to decode the three source floating point addition instruction which is to specify whether all of one or more floating point data elements of the third source operand are to be negated.

5. The processor of claim 3 , wherein the decode unit is to decode the three source floating point addition instruction which is to indicate the first, second, and third source operands which are respectively to have the first, second, and third floating point data elements as scalar data elements that are each to be stored in a respective packed data register that is also to be capable at different times to store packed data, and wherein the three source floating point addition instruction is to indicate a source predicate mask that is to have a mask element that is to correspond to, and is to predicate an operation of the three source floating point addition instruction on, the first, second, and third floating point data elements.

6. The processor of claim 3 , wherein the decode unit is to decode the three source floating point addition instruction which is to indicate the first, second, and third source operands which are respectively to have a first plurality of packed data elements that is to include the first floating point data element, a second plurality of packed data elements that is to include the second floating point data element, and a third plurality of packed data elements that is to include the third floating point data element.

7. The processor of claim 6 , wherein the decode unit is to decode the three source floating point addition instruction which is to indicate a source packed data operation mask that is to have a plurality of mask elements, each of the mask elements to correspond to, and to predicate a packed data operation of the three source floating point addition instruction on, corresponding floating point data elements of the first, second, and third source operands.

8. The processor of claim 3 , wherein the execution unit is to use a rounding mode for the first and second floating point rounded sums which is to be one of: (1) round to nearest with ties to even; (2) round down toward negative infinity; (3) round up toward positive infinity; and (4) round toward zero with truncate, and wherein the decode unit is to decode the three source floating point addition instruction which is to specify the rounding mode, and wherein the rounding mode which is to be specified by the three source floating point addition instruction is to override a rounding mode in a floating point control register of the processor.

9. The processor of claim 3 , wherein the execution unit comprises an output, an input, and circuitry coupling the output with the input.

10. The processor of claim 3 , wherein the decode unit is to decode the three source floating point addition instruction which is to have an enhanced vector extension (EVEX) encoding.

11. A processor comprising:
a plurality of registers;
a decode unit to decode a three source floating point addition instruction, the three source floating point addition instruction to indicate a first source operand that is to have at least a first floating point data element, to indicate a second source operand that is to have at least a second floating point data element, and to indicate a third source operand that is to have at least a third floating point data element; and
an execution unit coupled with the plurality of registers and the decode unit, the execution unit, in response to the three source floating point addition instruction, to store a result in a destination operand that is to be indicated by the three source floating point addition instruction, the result to include at least a result floating point data element that is to correspond to the first, second, and third floating point data elements, the result floating point data element to include a first floating point rounded sum, the first floating point rounded sum

Assignees

• Intel Corp

Inventors

• Espasa Roger
• Sole Guillem
• Fernandez Manel

Classifications

• G06F9/30038

  using a mask · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/30014

  with variable precision · CPC title