Indicating a length of an instruction of a variable length instruction set

Patent metadata

Field	Value
Publication number	US-9606931-B2
Application number	US-201113994695-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Some implementations disclosed herein provide techniques and arrangements for indicating a length of an instruction from an instruction set that has variable length instructions. A plurality of bytes that include an instruction may be read from an instruction cache based on a logical instruction pointer. A determination is made whether a first byte of the plurality of bytes identifies a length of the instruction. In response to detecting that the first byte of the plurality of bytes identifies the length of the instruction, the instruction is read from the plurality of bytes based on the length of the instruction.

First claim

What is claimed is:

1. A processor that includes one or more cores, at least one core of the one or more cores comprising:
an instruction cache; and
a pre-decode unit to:
read a first byte from the instruction cache using a logical instruction pointer that points to the first byte in the instruction cache;
detect whether the first byte includes a length of an instruction;
in response to detecting that the first byte includes the length of the instruction, read the instruction from the instruction cache based on the length of the instruction; and
in response to detecting that the first byte excludes the length of the instruction, detect the length of the instruction, and perform operations comprising modifying the first byte of the plurality of bytes to include the length of the instruction.

2. The processor of claim 1 , wherein the pre-decode unit is further to perform operations comprising:
detecting whether the first byte includes a value;
extracting the value from the first byte in response to detecting that the first byte includes the value; and
encoding the value based on an encoding scheme to create an encoded value.

3. The processor of claim 2 , wherein the pre-decode unit is further to perform operations comprising modifying the first byte to include the encoded value.

4. The processor of claim 1 , further comprising:
an instruction queue including a plurality of decoded instructions; and
an execution unit capable of executing the plurality of decoded instructions.

5. The processor of claim 4 , wherein the pre-decode unit is further to perform operations comprising placing the instruction in the instruction queue for execution by the execution unit.

6. The processor of claim 1 , wherein the pre-decode unit is further to:
read a prefix byte of the instruction from the instruction cache using the logical instruction pointer that points to the first byte in the instruction cache;

wherein the prefix byte to modify a behavior of the instruction.

7. A system that includes one or more processors, at least one of the one or more processors comprising:
an instruction cache; and
a pre-decode unit to:
read one or more bytes from the instruction cache starting at a byte pointed to by a logical instruction pointer,
determine whether the one or more bytes include a length of an instruction,
in response to detecting that the one or more bytes include the length of the instruction, extract the instruction from the one or more bytes based on the length, and
in response to detecting that the one or more bytes exclude the length of the instruction, determine the length of the instruction, extract the instruction from the one or more bytes based on the length of the instruction, and modify the one or more bytes to include the length of the instruction.

8. The system of claim 7 , further comprising:
an instruction queue to store instructions extracted from the instruction cache; and
an execution unit to execute at least one of the instructions extracted from the instruction queue.

9. The system of claim 8 , wherein the pre-decode unit is further to place the instruction in the instruction queue to enable the at least one of the one or more processors to execute the instruction.

10. The system of claim 7 , wherein:
the one or more bytes include a prefix byte of the instruction.

11. A method comprising:
reading, at a pre-decode unit of a processor, a plurality of bytes from an instruction cache based on a logical instruction pointer;
detecting whether a first byte of the plurality of bytes identifies a length of an instruction; and
in response to detecting that the first byte of the plurality of bytes excludes the length of the instruction,
determining the length of the instruction,
modifying the first byte of the plurality of bytes to include the length of the instruction, and
extracting the instruction from the plurality of bytes based on the length of the instruction.

12. The method of claim 11 , further comprising in response to detecting that the first byte of the plurality of bytes identifies the length of the instruction, extracting the instruction from the plurality of bytes based on the length of the instruction.

13. The method of claim 11 , wherein the length of the instruction is determined based on rules.

14. The method of claim 11 , further comprising:
detecting whether the first byte includes a value;
extracting the value from the first byte in response to detecting that the first byte includes the value;
encoding the value based on an encoding scheme to create an encoded value; and
modifying the first byte of the plurality of bytes to include the encoded value.

15. The method of claim 11 , further comprising placing the instruction in an instruction queue to enable execution of the instruction by an execution unit of the processor.

16. The method of claim 11 , wherein detecting whether the first byte of the plurality of bytes identifies the length of the instruction comprises:
identifying one or more indicator bits associated with the first byte; and
detecting whether the indicator bits indicate that the first byte includes the length of the instruction.

17. The method of claim 16 , wherein a prefix of the instruction comprises the one or more indicator bits.

18. The method of claim 11 , wherein the plurality of bytes comprise a prefix byte, the prefix byte to modify a behavior of the instruction.

Assignees

• Galan Santiago
• Espasa Roger
• Gago Julio
• Gonzalez Jose
• Intel Corp

Inventors

• Galan Santiago
• Espasa Roger
• Gago Julio
• Gonzalez Jose

Classifications

• G06F9/3017

  Runtime instruction translation, e.g. macros · CPC title

• G06F9/382

  Pipelined decoding, e.g. using predecoding · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/30152 Primary

  Determining start or end of instruction; determining instruction length · CPC title