Desai Shaishav A patents

• Multi-die systems with modular die-to-die link macros for enabling die-to-die communication

  US-2025378039-A1 · Dec 11, 2025 · US

• Digital phase-locked loops (PLL) including closed-loop time-to-digital converter (TDC) gain calibration circuits and related methods

  US-12463649-B2 · Nov 4, 2025 · US

• Digital phase-locked loops (pll) including closed-loop time-to-digital converter (tdc) gain calibration circuits and related methods

  US-2025141456-A1 · May 1, 2025 · US

• Domain clock and power activation control circuit to reduce voltage droop and related methods

  US-12019494-B2 · Jun 25, 2024 · US

• Peak voltage amplitude detectors tolerant to process variation and device mismatch and related methods

  US-11953527-B2 · Apr 9, 2024 · US

• Peak voltage amplitude detectors tolerant to process variation and device mismatch and related methods

  US-2024069074-A1 · Feb 29, 2024 · US

• Domain clock and power activation control circuit to reduce voltage droop and related methods

  US-2024004449-A1 · Jan 4, 2024 · US

• Digital signal processors providing scalable decision feedback equalization (DFE) employing sequence selection and related methods

  US-11838153-B1 · Dec 5, 2023 · US

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