Domain clock and power activation control circuit to reduce voltage droop and related methods

Patent metadata

Field	Value
Publication number	US-12019494-B2
Application number	US-202217853258-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jun 29, 2022
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A domain control circuit includes a power regulator to supply power for a first domain on a power rail and a sequencing circuit to control the power regulator, and a clock gate signal to activate the domain. The sequencing circuit receives a domain control signal to control activation and deactivation of the domain. The domain control circuit deactivates the clock gate signal to the domain after controlling the power regulator to supply power for the domain on a power rail. In this manner, a voltage droop in a supply voltage on a power rail is reduced. In some examples, the clock gate signal to the domain is deactivated after a voltage increase on the power rail. In some examples, the power regulator includes a plurality of parallel regulator circuits and a regulator control circuit to determine a number of the parallel regulator circuits to be activated to power the domain.

First claim

What is claimed is:

1. A domain control circuit, comprising:
a power regulator comprising a plurality of regulator circuits each configured to supply power on a power rail for a first domain of an integrated circuit (IC); and
a sequencing circuit configured to:
receive a domain control signal indicating one of activation and deactivation of the first domain; and
in response to the domain control signal indicating activation of the first domain:
generate a power control signal to control the plurality of regulator circuits to supply power on the power rail for the first domain; and
generate a clock gate signal in a first state to activate a clock signal in the first domain in response to the power control signal being generated to control the plurality of regulator circuits to supply power on the power rail for the first domain,

wherein the power regulator, further comprises a regulator control circuit configured to:
receive a power level signal; and
control a first plurality of regulator circuits of the plurality of regulator circuits to supply power in parallel to the power rail in response to the power control signal and the power level signal indicating a number of regulator circuits of the first plurality of regulator circuits to be activated.

2. The domain control circuit of claim 1 , wherein the sequencing circuit is further configured to generate the clock gate signal in the first state after generating the power control signal to control the plurality of regulator circuits to supply power on the power rail for the first domain.

3. The domain control circuit of claim 1 , wherein the sequencing circuit is further configured to generate the clock gate signal in the first state after a voltage on the power rail increases in response to the plurality of regulator circuits supplying power for the first domain.

4. The domain control circuit of claim 1 , each of the plurality of regulator circuits comprising:
a first transistor configured to couple a supply voltage node to an intermediate node based on the regulator control circuit; and
a second transistor configured to couple the intermediate node to the power rail based on a voltage on the power rail.

5. The domain control circuit of claim 1 , wherein the sequencing circuit is further configured to, in response to the domain control signal indicating deactivation of the first domain:
generate the clock gate signal in a second state to deactivate the clock signal in the first domain; and
generate the power control signal to control the plurality of regulator circuits to stop supplying power on the power rail for the first domain in response to generating the clock gate signal in the second state.

6. The domain control circuit of claim 5 , wherein the sequencing circuit is further configured to generate the power control signal to control the plurality of regulator circuits to stop supplying power on the power rail for the first domain at a predetermined delay interval after generating the clock gate signal in the second state.

7. The domain control circuit of claim 1 , the sequencing circuit further comprising:
a delay circuit comprising at least one buffer circuit configured to:
receive the domain control signal; and
generate a delayed domain control signal comprising the domain control signal delayed by a predetermined delay interval;

a first multiplexor configured to control the plurality of regulator circuits to supply power for the first domain in response to the domain control signal comprising a first state and the delayed domain control signal comprising the first state; and
a second multiplexor configured to generate the clock gate signal to deactivate the clock signal in the first domain in response to:
the domain control signal comprising the first state and the delayed domain control signal comprising a second state; and
the delayed domain control signal comprising the first state.

8. The domain control circuit of claim 1 , the power regulator further comprising at least one always-on regulator circuit for supplying power on the power rail for an always-on domain.

9. The domain control circuit of claim 1 , further comprising:
a second power regulator comprising a second plurality of regulator circuits configured to supply power on the power rail for a second domain of the IC;
a second sequencing circuit configured to:
receive a second domain control signal indicating one of activation and deactivation of the second domain:
in response to the second domain control signal indicating activation of the second domain:
generate a second power control signal to control the second plurality of regulator circuits to supply power on the power rail for the second domain; and
generate a second clock gate signal in the first state to activate a second clock signal in the second domain after generating the second power control signal to control the second plurality of regulator circuits to supply power on the power rail for the second domain.

10. A system comprising an integrated circuit (IC) comprising:
a first domain comprising a chip-to-chip interface circuit;
a domain control circuit, comprising:
a power regulator comprising a plurality of regulator circuits configured to supply power on a power rail for a first domain of an integrated circuit (IC); and
a sequencing circuit configured to:
receive a domain control signal indicating one of activation and deactivation of the first domain; and
in response to the domain control signal indicating activation of the first domain:
generate a power control signal to control the plurality of regulator circuits to supply power on the power rail for the first domain; and
generate a clock gate signal in a first state to activate a clock signal in the first domain after generating the power control signal to control the plurality of regulator circuits to supply power on the power rail for the first domain;

wherein the power regulator, further comprises a regulator control circuit configured to:
receive a power level signal; and
control a first plurality of regulator circuits of the plurality of regulator circuits to supply power in parallel to the power rail in response to the power control signal and the power level signal indicating a number of regulator circuits of the first plurality of regulator circuits to be activated; and

a clock distribution circuit configured to:
receive the clock gate signal;
receive a system clock signal; and
distribute the system clock signal to the first domain based on the clock gate signal.

11. The system of claim 10 , the IC further comprising an always-on domain configured to provide the domain control signal to the sequencing circuit.

12. The system of claim 11 , further comprising:
a second IC, comprising:
a second power regulator comprising a second plurality of regulator circuits configured to supply power on a second power rail for a second domain;
a second sequencing circuit configured to:
receive a second domain control signal indicating one of activation and deactivation of the second domain; and
in response to the second domain control signal indicating activation of the second domain:
generate a second power control signal to control the second plurality of regulator circuits to supply power on the second power rail for the second domain; and
generate a second clock gate signal in the first state to activate a second clock signal in the second domain after generating the second power control signal to control the second plurality of regulator circuits to supply power on the second power rail for the second domain.

13. A method of controlling

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Boecker Charles
• Groen Eric
• Desai Shaishav A

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title