Physical awareness of test-point sharing in a circuit design
US-12511462-B1 · Dec 30, 2025 · US
This page is not indexed by search engines while we improve data quality.
Chickermane Vivek patents
Chickermane Vivek is listed as an inventor on 30 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chickermane Vivek |
| Total patents | 30 |
| First publication | Oct 11, 2016 |
| Latest publication | Dec 30, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems and methods for reducing test point power consumption in a circuit design
US-12488176-B1 · Dec 2, 2025 · US
Clock-based test-point flop sharing in a circuit design
US-12475288-B1 · Nov 18, 2025 · US
Locking mechanism and core wrapping for IP core
US-12430474-B1 · Sep 30, 2025 · US
IC chip with IC design modification detection
US-12412014-B1 · Sep 9, 2025 · US
3D stacked die testing structure
US-12055586-B1 · Aug 6, 2024 · US
Test-point flop sharing with improved testability in a circuit design
US-11947887-B1 · Apr 2, 2024 · US
IC chip test engine
US-11379644-B1 · Jul 5, 2022 · US
IP block scan chain construction
US-11256839-B1 · Feb 22, 2022 · US
Method to improve testability using 2-dimensional exclusive or (XOR) grids
US-10955470-B1 · Mar 23, 2021 · US
Recent patents
Latest publications not already listed above.
Compacting test patterns for IJTAG test
US-10796041-B1 · Oct 6, 2020 · US
Low-power shift with clock staggering
US-10775435-B1 · Sep 15, 2020 · US
Method for optimally connecting scan segments in two-dimensional compression chains
US-10761131-B1 · Sep 1, 2020 · US
Test circuitry with annularly arranged compressor and decompressor elements
US-10747922-B1 · Aug 18, 2020 · US
Devices and methods for test point insertion coverage
US-10740515-B1 · Aug 11, 2020 · US
2D compression-based low power ATPG
US-10551435-B1 · Feb 4, 2020 · US
Verification process for IJTAG based test pattern migration
US-10528689-B1 · Jan 7, 2020 · US
Power and scan resource reduction in integrated circuit designs having shift registers
US-10417363-B1 · Sep 17, 2019 · US
SoC top-level XOR compactor design to efficiently test and diagnose multiple identical cores
US-10331506-B1 · Jun 25, 2019 · US
Optimizing core wrappers in an integrated circuit
US-10234504-B1 · Mar 19, 2019 · US
Method and system for construction of a highly efficient and predictable sequential test decompression logic
US-9817069-B1 · Nov 14, 2017 · US
Method and system for improving efficiency of sequential test compression using overscan
US-9817068-B1 · Nov 14, 2017 · US
Reducing mask data volume with elastic compression
US-9702934-B1 · Jul 11, 2017 · US
Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer
US-9606179-B1 · Mar 28, 2017 · US
Method for using XOR trees for physically efficient scan compression and decompression logic
US-9513335-B1 · Dec 6, 2016 · US
Systems and methods for testing integrated circuit designs
US-9501590-B1 · Nov 22, 2016 · US
Method for using sequential decompression logic for VLSI test in a physically efficient construction
US-9470756-B1 · Oct 18, 2016 · US
Method for dividing testable logic into a two-dimensional grid for physically efficient scan
US-9470755-B1 · Oct 18, 2016 · US
Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization
US-9470754-B1 · Oct 18, 2016 · US
Systems and methods for testing integrated circuit designs
US-9465896-B1 · Oct 11, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Cadence Design Systems Inc | 30 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F30/333 | 12 |
| G01R31/3177 | 12 |
| G01R31/318547 | 11 |
| G01R31/318583 | 7 |
| G01R31/318335 | 6 |