Method and system for improving efficiency of sequential test compression using overscan

Patent metadata

Field	Value
Publication number	US-9817068-B1
Application number	US-201514754386-A
Country	US
Kind code	B1
Filing date	Jun 29, 2015
Priority date	Jun 29, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Systems and methods efficiently bring additional variables into a Pseudo-Random Pattern Generator (“PRPG”) in the early cycles of an automatic test pattern generation (“ATPG”) process without utilizing any additional hardware or control pins. Overscanning (e.g., scanning longer than the length of the longest channel) for some additional cycles brings in enough variables into the PRPG. Data corresponding to earlier cycles of the ATPG process is removed.

First claim

What is claimed is:

1. A computer-implemented method for generating test patterns, the method comprising:
receiving, at a linear feedback shift register, a plurality of scan input signals;
updating bits in the linear feedback shift register using the plurality of scan input signals, each bit of the linear feedback shift register being shifted at each shift cycle for a plurality of shift cycles such that all of the bits in the linear feedback shift register are updated using the plurality of scan input signals, wherein a number of the plurality of shift cycles is greater than a number of scan channel bits of a longest scan channel, of a set of scan channels, by at least one;
feeding a set of outputs from the linear feedback shift register to a spreading network of XOR logic gates;
feeding a set of outputs from the spreading network to the set of scan channels, wherein the set of scan channels and each shift register of the linear feedback shift register are clocked at a same timing signal for the plurality of shift cycles; and
removing the outputs from the spreading network at a set of earliest scan cycles of the set of scan channels, wherein the set of the earliest scan cycles corresponds to shift cycles in which fewer than all of the bits in the linear feedback shift register were updated using the plurality of scan input signals.

2. The computer-implemented method of claim 1 , wherein, after each bit of the linear feedback shift register is shifted for a number of shift cycles corresponding to the number of scan channel bits of the longest scan channel, each bit is shifted for an additional number of shift cycles, wherein the additional number is less than: a total number of shift registers divided by a total number of scan input signals.

3. The computer-implemented method of claim 1 , wherein each bit of the linear feedback shift register is at an initial state before it is updated.

4. The computer-implemented method of claim 1 , wherein said removing is implemented based on the number of scan channel bits in each of the scan channels.

5. An automatic test pattern generation system, comprising:
a linear feedback shift register receiving one or more scan inputs from a tester, wherein the linear feedback shift register updates bits in the linear feedback shift register using the plurality of scan input signals, each bit of the linear feedback shift register being shifted at each shift cycle for a plurality of shift cycles such that all of the bits in the linear feedback shift register are updated using the plurality of scan input signals, wherein the number of the plurality of shift cycles is greater than a number of scan channel bits of a longest scan channel, of a set of scan channels, by at least one;
a spreading network of XOR logic gates, wherein the spreading network is configured to receive a set of outputs from the linear feedback shift register, wherein a set of outputs from the spreading network is output to a set of scan channels, wherein the set of scan channels and each shift register of the linear feedback shift register are clocked at a same timing signal for the plurality of shift cycles; and
a processor configured to remove the outputs from the spreading network at a set of earliest scan cycles of the set of scan channels, wherein the set of the earliest scan cycles corresponds to shift cycles in which fewer than all of the bits in the linear feedback shift register were updated using the plurality of scan input signals.

6. The automatic test pattern generation system of claim 5 , wherein, after each bit of the linear feedback shift register is shifted for a number of shift cycles corresponding to the number of scan channel bits of the longest scan channel, each bit is shifted for an additional number of shift cycles, wherein the additional number is less than a value equivalent to: a total number of shift registers divided by a total number of scan input signals.

7. The automatic test pattern generation system of claim 5 , wherein each bit of the linear feedback shift register is at an initial state before it is updated.

8. The automatic test pattern generation system of claim 5 , wherein the processor removes the outputs from the spreading network based on the number of scan channel bits in each of the scan channels.

9. A non-transitory computer readable medium containing program instructions for generating test patterns, wherein execution of the program instructions by one or more processors of a computer system causes one or more processors to carry out the steps of:
receiving, at a linear feedback shift register, a plurality of scan input signals, updating bits in the linear feedback shift register using the plurality of scan input signals, each bit of the linear feedback shift register being shifted at each shift cycle for a plurality of shift cycles such that all of the bits in the linear feedback shift register are updated using the plurality of scan input signals, wherein the number of the plurality of shift cycles is greater than a number of scan channel bits of a longest scan channel, of a set of scan channels, by at least one;
feeding a set of outputs from the linear feedback shift register to a spreading network of XOR logic gates;
feeding a set of outputs from the spreading network to the set of scan channels, wherein the set of scan channels and each shift register of the linear feedback shift register are clocked at a same timing signal for the plurality of shift cycles; and
removing the outputs from the spreading network at a set of earliest scan cycles of the set of scan channels, wherein the set of the earliest scan cycles corresponds to shift cycles in which fewer than all of the bits in the linear feedback shift register were updated using the plurality of scan input signals.

10. The non-transitory computer readable medium of claim 9 , wherein, after each bit of the linear feedback shift register is shifted for a number of shift cycles corresponding to the number of scan channel bits of the longest scan channel, each bit is shifted for an additional number of shift cycles, wherein the additional number is less than a value equivalent to: a total number of shift registers divided by a total number of scan input signals.

11. The non-transitory computer readable medium of claim 9 , wherein each bit of the linear feedback shift register is at an initial state before it is updated.

12. The non-transitory computer readable medium of claim 9 , wherein said removing is implemented based on the number of scan channel bits in each of the scan channels.

Assignees

• Cadence Design Systems Inc

Inventors

• Chickermane Vivek
• Chakravadhanula Krishna Vijaya
• Foutz Brian Edward
• Wilcox Steev
• Cunningham Paul Alexander
• Scott David George
• Milano Louis Christopher
• Meehl Dale Edward

Classifications

• G01R31/318544

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318335

  Test pattern compression or decompression (compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921) · CPC title

• G01R31/31813 Primary

  Test pattern generators · CPC title

• G01R31/31921

  using compression techniques, e.g. patterns sequencer · CPC title