Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization

Patent metadata

Field	Value
Publication number	US-9470754-B1
Application number	US-201514737331-A
Country	US
Kind code	B1
Filing date	Jun 11, 2015
Priority date	Jun 11, 2015
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide care bits in early scan cycles of the ATPG process for sequential decompressors starting from a fixed state.

First claim

What is claimed is:

1. An automatic test pattern generation system, comprising:
an elastic interface, configured to receive m scan inputs from a tester, wherein, in a first state, the elastic interface outputs the m scan inputs, and, in a second state, the elastic interface outputs i×m scan inputs, wherein i is an integer greater than 1;
a sequential decompressor receiving a plurality of outputs from the elastic interface;
a first combinational decompressor network receiving a plurality of outputs from the sequential decompressor; and
a plurality of scan channels receiving a plurality of outputs from the first combinational decompressor network.

2. The automatic test pattern generation system of claim 1 , further comprising:
at least one i-bit deserializer of the elastic interface, configured to receive a scan input of the m scan inputs from the tester; and
a multiplexer stage of the elastic interface including i multiplexers for each of the m scan inputs, each of the multiplexers having a first multiplexer input configured to receive the scan input of the m scan inputs, a second multiplexer input configured to receive an output of a shift register of the at least one i-bit deserializer, and a third multiplexer input configured to receive a control signal,
wherein the sequential decompressor receives one of the first and second multiplexer inputs, based on the control signal.

3. The automatic test pattern generation system of claim 1 , further comprising a second combinational decompressor network configured to receive the plurality of outputs from the elastic interface, and to provide a plurality of outputs to the sequential decompressor.

4. The automatic test pattern generation system of claim 1 , wherein each register bit inside of the sequential decompressor is shifted at each shift cycle for a total plurality of shift cycles that is greater than a length of a longest scan channel of the plurality of scan channels by at least one.

5. The automatic test pattern generation system of claim 1 , further comprising a processor configured to remove the outputs from the first combinational decompressor network at a set of earliest scan cycles of the plurality of scan channels, wherein the set of the earliest scan cycles corresponds to shift cycles in which not all register bits in the sequential decompressor had been updated using the plurality of outputs from the elastic interface.

6. The automatic test pattern generation system of claim 1 , further comprising:
a controller providing a control signal; and
a clock gate, configured to receive the control signal at a first input and a clock signal at a second input, and providing a clock output signal to enable or disable a shift into the plurality of scan channels.

7. The automatic test pattern generation system of claim 1 , wherein the sequential decompressor is one of (i) a linear shift register and (ii) a linear feedback shift register, and the first combinational decompressor network is at least one of (i) a linear spreader network of XOR logic gates and (ii) a broadcast scan distribution network.

8. A computer-implemented method of generating test patterns, the method comprising:
receiving, at an elastic interface, m scan inputs from a tester;
outputting, from the elastic interface, one of (i) the m scan inputs and (ii) i×m scan inputs to a plurality of inputs of a sequential decompressor, wherein i is an integer greater than 1;
updating, with a plurality of outputs of the elastic interface, bits in the sequential decompressor;
feeding a set of outputs from the sequential decompressor to a first combinational decompressor network; and
feeding a set of outputs from the first combinational decompressor network to a set of scan channels.

9. The computer-implemented method of claim 8 , further comprising:
receiving, at (i) at least one i-bit deserializer of the elastic interface and (ii) a first input of a multiplexer of a multiplexer stage of the elastic interface including i multiplexers, a scan input of the m scan inputs from the tester;
receiving, at a second input of the multiplexer, an output of a shift register of the i-bit deserializer;
receiving, at a third input of the multiplexer, a control signal; and
outputting one of the first and second multiplexer inputs to the plurality of inputs of the sequential decompressor based on the control signal.

10. The computer-implemented method of claim 8 , further comprising:
receiving, with a second combinational decompressor network, a plurality of outputs from the elastic interface;
feeding a set of outputs from the second combinational decompressor network to the plurality of inputs of the sequential decompressor; and
updating, with the set of outputs from the second combinational decompressor network, register bits resident in the sequential decompressor.

11. The computer-implemented method of claim 8 , wherein each register bit inside of the sequential decompressor is shifted at each shift cycle for a total plurality of shift cycles that is greater than a length of a longest scan channel of the set of scan channels by at least one.

12. The computer-implemented method of claim 8 , further comprising:
removing the outputs from the first combinational decompressor network at a set of earliest scan cycles of the set of scan channels, wherein the set of the earliest scan cycles corresponds to shift cycles in which not all register bits in the sequential decompressor had been updated using the plurality of outputs from the elastic interface.

13. The computer-implemented method of claim 8 , further comprising:
receiving, at a clock gate, a control signal from a controller at a first input and a clock signal at a second input; and
providing, with the clock gate, a clock output signal to enable or disable a shift into the set of scan channels.

14. The computer-implemented method of claim 8 , wherein the sequential decompressor is one of (i) linear shift register and (ii) a linear feedback shift register, and the first combinational decompressor network is at least one of (i) a linear spreader network of XOR logic gates and (ii) a broadcast scan distribution network.

15. A non-transitory computer readable medium containing program instructions for generating test patterns, wherein execution of the program instructions by one or more processors of a computer system causes one or more processors to perform the following:
receive, at an elastic interface, m scan inputs from a tester;
output, from the elastic interface, one of (i) the m scan inputs and (ii) i×m scan inputs to a plurality of inputs of a sequential decompressor, wherein i is an integer greater than 1;
update, with a plurality of outputs of the elastic interface, register bits resident inside the sequential decompressor;
feed a set of outputs from the sequential decompressor to a first combinational decompressor network; and
feed a set of outputs from the first combinational decompressor network to a set of scan channels.

16. The non-transitory computer readable medium of claim 15 , wherein execution of the program instructions by one or more processors of a computer system further causes one or more processors to perform the following:
receive, at (i) at least one i-bit deserializer of the elastic interface and (ii) a first input of a multiplexer of a multiplexer stage of the elastic interface including i multiplexers, a scan input of the m scan inputs from the tester;
receive, at a second input of the multiplexer, an output of a shift register of the i-bit deserializer;
receive, at a third input of the mul

Assignees

• Cadence Design Systems Inc

Inventors

• Chickermane Vivek
• Chakravadhanula Krishna Vijaya
• Foutz Brian Edward
• Wilcox Steev
• Cunningham Paul Alexander
• Scott David George
• Milano Louis Christopher
• Meehl Dale Edward

Classifications

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318335 Primary

  Test pattern compression or decompression (compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921) · CPC title

• G01R31/318547

  Data generators or compressors · CPC title