Clock-based test-point flop sharing in a circuit design

Patent metadata

Field	Value
Publication number	US-12475288-B1
Application number	US-202217953693-A
Country	US
Kind code	B1
Filing date	Sep 27, 2022
Priority date	Sep 27, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group. The test-point flop allocation module can further allocate one of the test-point flops to each of the test-point sharing groups. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design based on the circuit netlist. The circuit layout is employable to fabricate an IC chip.

First claim

What is claimed is:

1 . A system comprising:
a non-transitory memory that stores machine-readable instructions and receives a circuit netlist associated with a circuit design, the circuit netlist comprising functional logic, test-point nodes coupled to portions of the functional logic, a plurality of clock-gates, and a plurality of test-point flops associated with scan-chains; and a processing unit that accesses the memory and executes the machine-readable instructions, the machine-readable instructions comprising an electronic design automation (EDA) application, the EDA application comprising:
a test-point flop allocation module that is configured to divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group, the test-point flop allocation module being further configured to allocate one of the test-point flops to each of the test-point sharing groups in the circuit netlist; and
a circuit layout module configured to generate a circuit layout associated with the circuit design based on the circuit netlist.

2 . The system of claim 1 , wherein the test-point flop allocation module is configured to trace input/output connections backwards on the circuit netlist from the test-point node to an output of each of the at least one flip-flop in the portion of the functional logic, from a clock input of each of the at least one flip-flop to an output of each of the clock-gates, and from an input of each of the clock-gates to a clock signal that defines an associated clock domain to determine the respective one of the clock-gates that is common to each of the at least one flip-flop of the portion of the functional logic.

3 . The system of claim 2 , wherein the test-point flop allocation module selects the respective one of the clock-gates that is most directly coupled to the at least one flip-flop of the portion of the functional logic in response to the test-point flop allocation module determining multiple clock-gates common to each of the at least one flip-flop of the portion of the functional logic.

4 . The system of claim 1 , wherein the test-point flop allocation module is further configured to subdivide the test-point nodes in the test-point sharing groups into smaller test-point sharing groups based on functional hierarchy tiers defined in the circuit netlist.

5 . The system of claim 1 , wherein the test-point flop allocation module is further configured to assign a clock signal to the test-point flop associated with each of the test-point sharing groups, the clock signal being output from the respective one of the clock-gates that is common to each of the at least one flip-flop of the portion of the functional logic coupled to the test-point nodes of the respective one of the test-point sharing groups, wherein the circuit layout module is configured to arrange the test-point flops proximal to the test-point nodes of the respective one of test-point sharing groups on the circuit layout based on the assignment of the clock signal from the respective one of the clock-gates.

6 . The system of claim 1 , wherein, in response to a quantity of the test-point sharing groups being less than a quantity of the test-point flops, the test-point flop allocation module is further configured to subdivide the test-point nodes in the test-point sharing groups into smaller test-point sharing groups based on functional hierarchy tiers defined in the circuit netlist.

7 . The system of claim 6 , wherein the test-point flop allocation module is further configured to assign a clock signal to the test-point flop associated with each of the test-point sharing groups, the clock signal being output from a respective one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to the test-point nodes of the respective one of the test-point sharing groups.

8 . The system of claim 1 , wherein, in response to the circuit layout module generating the circuit layout, the circuit layout module is further configured to receive user inputs to facilitate relocation of each of the test-point flops proximal to a respective one of the test-point sharing groups in the circuit layout of the circuit design.

9 . The system of claim 8 , wherein the circuit layout module is further configured to provide interconnects between the relocated test-point flops in the circuit layout to form the scan-chains.

10 . A non-transitory computer readable medium comprising machine-readable instructions, the machine-readable instructions being executed to:
receive, at a circuit design tool executing on a computing platform, a circuit netlist associated with a circuit design, the circuit netlist comprising functional logic, test-point nodes coupled to portions of the functional logic, a plurality of clock-gates, and a plurality of test-point flops associated with scan-chains; divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group via a test-point flop allocation module executing on the computing platform; allocate one of the test-point flops to each of the test-point sharing groups in the circuit netlist via the test-point flop allocation module executing on the computing platform; and generate a circuit layout associated with the circuit design via a circuit layout module executing on the computing platform based on the circuit netlist, wherein the circuit layout is employable to fabricate an integrated circuit (IC) chip.

11 . The medium of claim 10 , wherein the test-point flop allocation module is configured to trace input/output connections backwards on the circuit netlist from the test-point node to an output of each of the at least one flip-flop in the portion of the functional logic, from a clock input of each of the at least one flip-flop to an output of each of the clock-gates, and from an input of each of the clock-gates to a clock signal that defines an associated clock domain to determine the respective one of the clock-gates that is common to each of the at least one flip-flop of the portion of the functional logic.

12 . The medium of claim 11 , wherein the test-point flop allocation module selects the respective one of the clock-gates that is most directly coupled to the at least one flip-flop of the portion of the functional logic in response to the test-point flop allocation module determining multiple clock-gates common to each of the at least one flip-flop of the portion of the functional logic.

13 . The medium of claim 10 , wherein, in response to a quantity of the test-point sharing groups being less than a quantity of the test-point flops, the test-point flop allocation module is further configured to subdivide the test-point nodes in the test-point sharing groups into smaller test-point sharing groups based on functional hierarchy tiers defined in the circuit netlist.

14 . The medium of claim 13 , wherein the test-point flop allocation module is further configured to assign a clock signal to the test-point flop associated with each of the test-point sharing groups, the clock signal being output from a respective one of the clock-gates that is common to each of at least one flip-flop

Assignees

• Cadence Design Systems Inc

Inventors

• Foutz Brian
• Chickermane Vivek
• Nandakumar Bharath
• Chillarige Sameer Chakravarthy
• Chakravadhanula Krishna
• Rai Prateek Kumar
• Singhal Sarthak

Classifications

• G01R31/31704

  Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00) · CPC title

• G01R31/318583

  Design for test · CPC title

• G06F30/333 Primary

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/323 Primary

  Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation · CPC title