Reducing mask data volume with elastic compression

Patent metadata

Field	Value
Publication number	US-9702934-B1
Application number	US-201514921769-A
Country	US
Kind code	B1
Filing date	Oct 23, 2015
Priority date	Jun 11, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Systems and methods disclosed herein provide for efficiently loading mask data to the mask register bits from the decompression network outputs of an ATPG system. The systems and methods also provide an elastic interface utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the number of input variables utilized during the loading of the mask data to the mask register bits.

First claim

What is claimed is:

1. A system for loading a mask flop bit register of an automatic test pattern generation system,
comprising:
a sequential decompressor configured to receive m scan inputs;
a combinational decompressor network configured to receive a plurality of outputs from the sequential decompressor, wherein the mask flop bit register is configured to directly receive a plurality of outputs from the combinational decompressor network.

2. The system of claim 1 , further comprising:
an interface, configured to receive the m scan inputs and provide a plurality of outputs to the sequential decompressor, wherein, in a first state, the interface outputs the m scan inputs, and, in a second state, the interface outputs i×m scan inputs, wherein i is an integer greater than 1.

3. The system of claim 2 , further comprising:
at least one i-bit deserializer of the interface, configured to (i) receive the m scan inputs and (ii) output one of the m scan inputs and the i×m scan inputs based on a control signal.

4. The system of claim 2 , further comprising a second combinational decompressor network configured to receive the plurality of outputs from the interface, and to provide a plurality of outputs to the sequential decompressor.

5. The system of claim 1 , wherein the mask flop bit register is configured to update bits in the mask flop bit register using the outputs from the combinational decompressor network.

6. The system of claim 1 , further comprising:
a second mask flop bit register.

7. The system of claim 6 , wherein (i) the mask flop bit register is configured to update bits in the mask flop bit register using the outputs from the combinational decompressor network and (ii) the second mask flop bit register is configured to receive a plurality of values corresponding to the updated bits from the mask flop bit register and update bits in the second mask flop bit register using the plurality of values from the mask flop bit register.

8. The system of claim 6 , wherein, in a first step, the mask flop bit register updates bits in the mask flop bit register using the outputs from the combinational decompressor network and, in a second step, the second mask flop bit register (i) receives a plurality of outputs from the combinational decompressor network and (ii) updates bits in the mask flop bit register using the outputs from the combinational decompressor network.

9. A computer-implemented method of loading a mask flop bit register of an automatic test pattern generation system, the method comprising:
receiving, at a sequential decompressor, m scan inputs;
updating, with the m scan inputs, bits in the sequential decompressor;
feeding a set of outputs from the sequential decompressor to a combinational decompressor network; and
feeding a set of outputs from the combinational decompressor network directly to the mask flop bit register.

10. The computer-implemented method of claim 9 , further comprising:
receiving, at an interface, the m scan inputs from a tester; and
outputting, from the interface, one of (i) the m scan inputs and (ii) i×m scan inputs to a plurality of inputs of the sequential decompressor, wherein i is an integer greater than 1.

11. The computer-implemented method of claim 10 , further comprising:
receiving, with at least one i-bit deserializer of the interface, the m scan inputs from the tester; and
outputting one of the m scan inputs and the i×m scan inputs based on a control signal.

12. The computer-implemented method of claim 10 , further comprising:
receiving, with a second combinational decompressor network, a plurality of outputs from the interface;
feeding a set of outputs from the second combinational decompressor network to the plurality of inputs of the sequential decompressor; and
updating, with the set of outputs from the second combinational decompressor network, register bits resident in the sequential decompressor.

13. The computer-implemented method of claim 9 , further comprising:
updating bits in the mask flop bit register using the outputs from the combinational decompressor network.

14. The computer-implemented method of claim 9 , further comprising:
updating bits in the mask flop bit register using the outputs from the combinational decompressor network;
receiving, with a second mask flop bit register, a plurality of values corresponding to the updated bits in the mask flop bit register; and
updating, with the second mask flop bit register, bits in the second mask flop bit register using the plurality of values from the mask flop bit register.

15. The computer-implemented method of claim 9 , further comprising:
updating bits in the mask flop bit register using the outputs from the combinational decompressor network;
receiving, with a second mask flop bit register, a plurality of outputs from the combinational decompressor network, and
updating, with the second mask flop bit register, bits in the second mask flop bit register using the outputs from the combinational decompressor network.

16. A non-transitory computer readable medium containing program instructions for loading a mask flop bit register of an automatic test pattern generation system, wherein execution of the program instructions by one or more processors of a computer system causes one or more processors to perform the following:
receive, at a sequential decompressor, m scan inputs;
update, with the m scan inputs, bits in the sequential decompressor;
feed a set of outputs from the sequential decompressor to a combinational decompressor network; and
feed a set of outputs from the combinational decompressor network directly to the mask flop bit register.

17. The non-transitory computer readable medium of claim 16 , wherein execution of the program instructions by one or more processors of a computer system further causes one or more processors to perform the following:
receive, at an interface, the m scan inputs from a tester; and
output, from the interface, one of (i) the m scan inputs and (ii) i×m scan inputs to a plurality of inputs of the sequential decompressor, wherein i is an integer greater than 1.

18. The non-transitory computer readable medium of claim 16 , wherein execution of the program instructions by one or more processors of a computer system further causes one or more processors to perform the following:
update bits in the mask flop bit register using the outputs from the combinational decompressor network.

19. The non-transitory computer readable medium of claim 16 , wherein execution of the program instructions by one or more processors of a computer system further causes one or more processors to perform the following:
update bits in the mask flop bit register using the outputs from the combinational decompressor network;
receive, with a second mask flop bit register, a plurality of values corresponding to the updated bits in the mask flop bit register; and
update, with the second mask flop bit register, bits in the second mask flop bit register using the plurality of values from the mask flop bit register.

20. The non-transitory computer readable medium of claim 16 , wherein execution of the program instructions by one or more processors of a computer system further causes one or more processors to perform the following:
update bits in the mask flop bit register using the outputs from the combinational decompressor network;
receive, with a second mask flop bit register, a plurality of outputs from the combinational decompressor network, and
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Assignees

• Cadence Design Systems Inc

Inventors

• Meehl Dale Edward
• Chickermane Vivek

Classifications

• G01R31/318335 Primary

  Test pattern compression or decompression (compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921) · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318547

  Data generators or compressors · CPC title