Dynamic multilevel memory system
US-12430057-B2 · Sep 30, 2025 · US
This page is not indexed by search engines while we improve data quality.
Chen Wei P patents
Chen Wei P is listed as an inventor on 23 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chen Wei P |
| Total patents | 23 |
| First publication | Feb 7, 2019 |
| Latest publication | Sep 30, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Selective fill for logical control over hardware multilevel memory
US-12386748-B2 · Aug 12, 2025 · US
Distribution of error checking and correction (ECC) bits to allocate ECC bits for metadata
US-12373287-B2 · Jul 29, 2025 · US
Two-level main memory hierarchy management
US-12271305-B2 · Apr 8, 2025 · US
Fast memory ECC error correction
US-12242342-B2 · Mar 4, 2025 · US
Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)
US-12235720-B2 · Feb 25, 2025 · US
Adaptive error correction to improve system memory reliability, availability, and serviceability (ras)
US-2024061741-A1 · Feb 22, 2024 · US
Memory system, computing system, and methods thereof for cache invalidation with dummy address space
US-11580029-B2 · Feb 14, 2023 · US
Memory utilized as both system memory and near memory
US-11567877-B2 · Jan 31, 2023 · US
Embedded controller and memory to store memory error information
US-2022350500-A1 · Nov 3, 2022 · US
Recent patents
Latest publications not already listed above.
Dynamic multilevel memory system
US-2022229575-A1 · Jul 21, 2022 · US
Selective fill for logical control over hardware multilevel memory
US-2022222178-A1 · Jul 14, 2022 · US
Hardware unit for reverse translation in a processor
US-11307996-B2 · Apr 19, 2022 · US
Fast memory ecc error correction
US-2022107866-A1 · Apr 7, 2022 · US
Method and apparatus to reduce power consumption for refresh of memory devices on a memory module
US-11250902-B2 · Feb 15, 2022 · US
Memory system, computing system, and methods thereof
US-2021263855-A1 · Aug 26, 2021 · US
Two-level main memory hierarchy management
US-2021216452-A1 · Jul 15, 2021 · US
Distribution of error checking and correction (ecc) bits to allocate ecc bits for metadata
US-2021141692-A1 · May 13, 2021 · US
Memory system, computing system, and methods thereof for cache invalidation with dummy address space
US-10997082-B2 · May 4, 2021 · US
Method and apparatus to reduce power consumption for refresh of memory devices on a memory module
US-2020027500-A1 · Jan 23, 2020 · US
Memory system, computing system, and methods thereof
US-2019310944-A1 · Oct 10, 2019 · US
Memory utilized as both system memory and near memory
US-2019258583-A1 · Aug 22, 2019 · US
Memory module designed to conform to a first memory chip specification having memory chips designed to conform to a second memory chip specification
US-2019042095-A1 · Feb 7, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 23 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F2212/1024 | 7 |
| Y02D10/00 | 7 |
| G06F11/1048 | 7 |
| G06F12/0871 | 6 |
| G06F12/0897 | 6 |