Memory system, computing system, and methods thereof for cache invalidation with dummy address space

Patent metadata

Field	Value
Publication number	US-10997082-B2
Application number	US-201916451086-A
Country	US
Kind code	B2
Filing date	Jun 25, 2019
Priority date	Jun 25, 2019
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

First claim

What is claimed is:

1. A memory system, comprising:
a memory having a memory address space associated therewith to access the memory;
a cache memory assigned to the memory; and
one or more processors configured to:
generate a dummy address space in addition to the memory address space,
wherein each address of the dummy address space is distinct from any address of the memory address space, and

invalidate one or more cache entries in the cache memory by having the one or more invalid cache entries reference the dummy address space.

2. The memory system of claim 1 ,
wherein each invalid cache entry of the one or more invalid cache entries comprises a tag, and
wherein each tag of the one or more invalid cache entries represents a respective dummy address of the dummy address space.

3. The memory system of claim 1 ,
wherein the one or more processors are configured to invalidate the one or more cache entries by a dummy read operation directed to one or more dummy addresses of the dummy address space.

4. The memory system of claim 1 ,
wherein the one or more processors are further configured to generate one or more valid cache entries in the cache memory, and
wherein the one or more valid cache entries reference one or more memory addresses of the memory address space.

5. The memory system of claim 1 ,
wherein the one or more processors are further configured to change a bit-value of a dirty bit associated with each cache entry of the cache memory that is modified by a write-back operation.

6. The memory system of claim 1 ,
wherein the dummy address space is associated with a memory size that is substantially equal to a memory size of the cache memory.

7. The memory system of claim 1 ,
wherein a number of dummy addresses of the dummy address space is greater than or equal to a maximum number of cache entries of the cache memory.

8. The memory system of claim 1 ,
wherein a memory size of the memory is greater than a memory size of the cache memory.

9. The memory system of claim 1 ,
wherein a latency for an input/output operation directed to the memory is greater than a latency for an input/output operation directed to the cache memory.

10. The memory system of claim 1 ,
wherein a bandwidth for an input/output operation directed to the memory is less than a bandwidth for an input/output operation directed to the cache memory.

11. The memory system of claim 1 ,
wherein a memory size of the memory is an integer multiple of a memory size of the cache memory.

12. The memory system of claim 1 ,
wherein the cache memory comprises one or more random access memory modules.

13. The memory system of claim 1 ,
wherein the memory comprises one or more random access memory modules.

14. The memory system of claim 1 ,
wherein the one or more processors are further configured to:
determine a memory size of the cache memory and
generate the dummy address space with a predefined size, and

wherein the predefined size is dependent from the determined memory size of the cache memory.

15. The memory system of claim 1 ,
wherein the one or more processors are further configured to:
determine a memory size of the cache memory, and
generate the dummy address space with a size that matches the determined memory size of the cache memory.

16. The memory system of claim 1 ,
wherein the dummy address space is not accessible by a read operation from an application executed by an operating system of a computing system coupled to the memory system.

17. A computing system, comprising:
a memory having a memory address space associated therewith to access the memory;
a cache memory assigned to the memory; and
one or more processors configured to:
access the memory via memory addresses of the memory address space,
generate a dummy address space in addition to the memory address space,
wherein each address of the dummy address space is distinct from any address of the memory address space, and

invalidate one or more cache entries in the cache memory by having the one or more invalid cache entries reference the dummy address space.

18. The computing system of claim 17 ,
wherein the one or more processors are configured to execute an operating system and/or applications,
wherein the operating system and/or the applications are configured to:
permit access to the memory through the cache memory, and
preclude access to dummy addresses of the dummy address space.

19. A method of a memory system comprising a memory having a memory address space associated therewith to access the memory and a cache memory assigned to the memory, the method comprising:
generating a dummy address space,
wherein the dummy address space has a memory size that is greater than or equal to a memory size of the cache memory;

providing a dummy read instruction to read from each address of the dummy address space; and
in response to the dummy read operation, replacing a plurality of cache entries in the cache memory with a plurality of invalid cache entries referencing the dummy address space.

20. The method of claim 19 , further comprising:
in response to the dummy read operation, flushing a dirty cache entry to the memory before the dirty cache entry is replaced by an invalid cache entry of the plurality of invalid cache entries.

Assignees

• Intel Corp

Inventors

• Rudoff Andy
• Kasanicky Tiffany J
• Chen Wei P
• Agarwal Rajat
• Douglas Chet R

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F12/023

  Free address space management · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0891 Primary

  using clearing, invalidating or resetting means · CPC title