Selective fill for logical control over hardware multilevel memory

Patent metadata

Field	Value
Publication number	US-12386748-B2
Application number	US-202217710806-A
Country	US
Kind code	B2
Filing date	Mar 31, 2022
Priority date	Mar 31, 2022
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A system includes a multilevel memory such as a two level memory (2LM), where a first level memory acts as a cache for the second level memory. A memory controller or cache controller can detect a cache miss in the first level memory for a request for data. Instead of automatically performing a swap, the controller can determine whether to perform a swap based on a swap policy assigned to a memory region associated with the address of the requested data.

First claim

What is claimed is:

1. An apparatus for memory management, comprising:
a multilevel memory having a first level memory and a second level memory, the first level memory to cache data for the second level memory, the second level memory having an address space with multiple memory regions, with different swap policies assigned to different memory regions, where different swap policies define factors to determine when data in the second level memory is to be swapped with data in the first level memory, moving data from the second level memory into the first level memory, replacing data in the first level memory that is moved into the second level memory; and
a memory controller coupled to the multilevel memory, the memory controller to detect a cache miss in the first level memory on a request for requested data, identify a specific memory region associated with an address of the requested data, and determine whether to swap the requested data from the second level memory to the first level memory in response to the cache miss, based on a swap policy assigned to the specific memory region.

2. The apparatus of claim 1 , wherein the specific memory region comprises an address range.

3. The apparatus of claim 1 , wherein the specific memory region comprises a physical page.

4. The apparatus of claim 1 , wherein the memory controller is to maintain an access counter per memory region to determine how hot the memory region is, and wherein the memory controller is to swap the requested data from the second level memory to the first level memory based on the swap policy assigned to the specific memory region and how hot the memory region is.

5. The apparatus of claim 4 , wherein the access counter comprises a leaky bucket counter per memory region, with a higher counter value to indicate a hotter memory region, the leaky bucket counter to increment for each cache miss within the memory region, and to decrement based on time.

6. The apparatus of claim 1 , wherein the swap policy comprises a no swap policy to indicate no cache fill, preventing eviction from the first level memory for the specific memory region.

7. The apparatus of claim 1 , wherein the swap policy comprises a full swap policy to indicate a swap of the requested data in response to the cache miss.

8. The apparatus of claim 1 , wherein the swap policy comprises a lazy fill swap policy to indicate a swap of the specific memory region in response to the cache miss for the requested data, but only portion-by-portion as requests are made for portions of the specific memory region.

9. The apparatus of claim 1 , wherein the first level memory comprises volatile memory and the second level memory comprises persistent memory.

10. A computer system with memory management, comprising:
a multilevel memory having a first level memory and a second level memory, the first level memory to cache data for the second level memory, the second level memory having an address space with multiple memory regions, with different swap policies assigned to different memory regions, where different swap policies define factors to determine when data in the second level memory is to be swapped with data in the first level memory, moving data from the second level memory into the first level memory, replacing data in the first level memory that is moved into the second level memory;
a processor to execute a host operating system, the host operating system to generate a memory access request for requested data stored in the multilevel memory; and
a memory controller coupled to the multilevel memory and the processor, the memory controller to detect a cache miss in the first level memory in response to the memory access request, identify a specific memory region associated with an address of the requested data, and determine whether to swap the requested data from the second level memory to the first level memory in response to the cache miss, based on a swap policy assigned to the specific memory region.

11. The computer system of claim 10 , wherein the specific memory region comprises an address range or a physical page.

12. The computer system of claim 10 , wherein the memory controller is to maintain an access counter per memory region to determine how hot the memory region is, and wherein the memory controller is to swap the requested data from the second level memory to the first level memory based on the swap policy assigned to the specific memory region and how hot the memory region is.

13. The computer system of claim 10 , wherein the swap policy comprises a no swap policy to indicate no cache fill, preventing eviction from the first level memory for the specific memory region.

14. The computer system of claim 10 , wherein the swap policy comprises a full swap policy to indicate a swap of the requested data in response to the cache miss.

15. The computer system of claim 10 , wherein the swap policy comprises a lazy fill swap policy to indicate a swap of the specific memory region in response to the cache miss for the requested data, but only page-by-page as requests are made for pages of the specific memory region.

16. The computer system of claim 10 , including one or more of:
wherein the processor comprises a multicore processor;
a display communicatively coupled to the processor; or
a network interface communicatively coupled to the processor.

17. A method for memory management, comprising:
receiving a memory access request for requested data stored in a multilevel memory having a first level memory and a second level memory, the first level memory to cache data for the second level memory, the second level memory having an address space with multiple memory regions, with different swap policies assigned to different memory regions, where different swap policies define factors to determine when data in the second level memory is to be swapped with data in the first level memory, moving data from the second level memory into the first level memory, replacing data in the first level memory that is moved into the second level memory;
detecting a cache miss in the first level memory in response to the memory access request;
identifying a specific memory region associated with an address of the requested data; and
determining whether to swap the requested data from the second level memory to the first level memory in response to the cache miss, based on a swap policy assigned to the specific memory region.

18. The method of claim 17 , wherein the specific memory region comprises an address range or a physical page.

19. The method of claim 17 , further comprising:
maintaining an access counter per memory region to determine how hot the memory region is, and wherein swapping the requested data from the second level memory to the first level memory is based on the swap policy assigned to the specific memory region and how hot the memory region is, and wherein the access counter comprises a leaky bucket counter per memory region, with a higher counter value to indicate a hotter memory region, the leaky bucket counter to increment for each cache miss within the memory region, and to decrement based on time.

20. The method of claim 17 , wherein performing the swap comprises selecting from among multiple swap policies, including a lazy fill swap policy to indicate a swap of the specific memory region in response to the cache miss for the requested data, but only cacheline by cacheline as requests are made for cachelines of the specific memory region.

Assignees

• Intel Corp

Inventors

• Agarwal Rajat
• Muralidhara Sai Prashanth
• Chen Wei P
• Singh Nishant
• Venkateswaran Sharada
• Liu Daniel W

Classifications

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title