Hardware unit for reverse translation in a processor

Patent metadata

Field	Value
Publication number	US-11307996-B2
Application number	US-201816206516-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	Nov 30, 2018
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processing engines (PEs) to execute threads; and
a reverse translation circuit to:
read, from a non-volatile storage included in a memory module, a module address of a corrupt portion of the memory module;
determine a plurality of system physical address (SPA) addresses associated with the memory module;
translate the plurality of SPA addresses into a plurality of translated module addresses, wherein a mapping between the plurality of SPA addresses and the plurality of translated module addresses is changed by one or more system events;
determine whether a first translated module address of the plurality of translated module addresses matches the module address of the corrupt portion of the memory module, wherein the first translated module address was translated from a first SPA address; and
in response to a determination that the first translated module address matches the module address of the corrupt portion of the memory module, identify the first SPA address as a current address of the corrupt portion of the memory module.

2. The processor of claim 1 , wherein the reverse translation circuit is implemented in a patrol scrub engine.

3. The processor of claim 2 , wherein the reverse translation circuit uses iterative logic of the patrol scrub engine to loop through the plurality of SPA addresses.

4. The processor of claim 1 , the reverse translation circuit to, in response to the determination that the translated module address matches the module address of the corrupt portion of the memory module:
store the first SPA address in a register; and
set a completion flag indicating that a reverse translation of the module address of the corrupt portion of the memory module is completed.

5. The processor of claim 1 , the reverse translation circuit to determine the module address of the corrupt portion in response to a detection of a trigger condition associated with reverse translation, wherein the trigger condition comprises at least one selected from a system a reboot, a request from an operating system, a request from platform firmware, a request from a driver, a user command, and a system start-up.

6. The processor of claim 1 , wherein the plurality of SPA addresses is a range of SPA addresses associated with a channel coupled to the memory module, wherein the range of SPA addresses is specified by Basic Input/Output System (BIOS) firmware.

7. The processor of claim 1 , wherein the non-volatile storage comprises a Serial Presence Detect (SPD) storage included in the memory module, and wherein the memory module comprises volatile system memory.

8. The processor of claim 1 , wherein the module address of the corrupt portion of the memory module comprises a rank identifier, a bank identifier, a row identifier, and a column identifier.

9. A method comprising:
detecting a trigger condition associated with reverse translation, wherein the trigger condition comprises at least one selected from a system start-up, a reboot, a request from an operating system, a request from platform firmware, a request from a driver, and a user command;
in response to detecting the trigger condition:
determining, by a reverse translation circuit included in a processor, a module address of a corrupt portion of a memory module;
determining, by the reverse translation circuit, a range of system physical address (SPA) addresses associated with the memory module;
performing, by the reverse translation circuit, a plurality of iterations based on the range of SPA addresses, each iteration comprising:
translating a unique SPA address into a translated module address; and
in response to a determination that the translated module address matches the module address of the corrupt portion of the memory module, identifying the unique SPA address as a current address of the corrupt portion of the memory module.

10. The method of claim 9 , further comprising:
in response to the determination that the translated module address matches the module address of the corrupt portion:
storing the unique SPA address in a register; and
setting a completion flag to indicate that a reverse translation of the module address of the corrupt portion is completed.

11. The method of claim 9 , wherein the reverse translation circuit is included in a patrol scrub engine of the processor.

12. The method of claim 11 , wherein performing the plurality of iterations comprises using iterative logic of the patrol scrub engine to loop through the range of SPA addresses.

13. The method of claim 9 , wherein determining the module address of the corrupt portion comprises reading the module address of the corrupt portion from a Serial Presence Detect (SPD) storage included in the memory module.

14. The method of claim 13 , further comprising:
receiving, by system software, a SPA address associated with an uncorrectable error in the memory module;
translating, by the system software, the received SPA address into the module address of the corrupt portion; and
storing, by the system software, the module address of the corrupt portion in the SPD storage in the memory module.

15. The method of claim 9 , further comprising:
in response to the determination that the translated module address matches the module address of the corrupt portion:
storing the unique SPA address in a register; and
using, by an operating system, the stored unique SPA address to prevent an allocation of the corrupt portion into a memory address space.

16. A system comprising:
a processor comprising a plurality of processing engines and a memory controller, the memory controller to:
read, from a non-volatile storage included in a memory module, a module address of a corrupt portion of a memory module; and
determine a plurality of system physical address (SPA) addresses associated with the memory module;
translate the plurality of SPA addresses into a plurality of translated module addresses, wherein a mapping between the plurality of SPA addresses and the plurality of translated module addresses is changed by one or more system events;
determine whether a first translated module address of the plurality of translated module addresses matches the module address of the corrupt portion of the memory module, wherein the first translated module address was translated from a first SPA address; and
in response to a determination that the first translated module address matches the module address of the corrupt portion of the memory module, identify the first SPA address as a current address of the corrupt portion of the memory module; and

a system memory coupled to the processor.

17. The system of claim 16 , wherein the memory controller comprises a patrol scrub engine, and wherein the memory controller uses iterative logic of the patrol scrub engine to loop through the plurality of SPA addresses.

18. The system of claim 16 , the memory controller to identify the module address of the corrupt portion in response to a detection of a trigger condition associated with reverse translation, wherein the trigger condition comprises at least one selected from a system a reboot, a request from an operating system, a request from platform firmware, a request from a driver, a user command, and a system start-up.

19. The system of claim 16 , wherein the non-volatile storage comprises a Serial Presence Detect (SPD) storage included in the memory module, and wherein the memory module comprises volatile system memory.

20. The syste

Assignees

• Intel Corp

Inventors

• Jayakumar Sarathy
• Raj Ashok
• Chen Wei P
• Yigzaw Theodros
• Holm John

Classifications

• G06F11/2284

  by power-on test, e.g. power-on self test [POST] · CPC title

• G06F13/1694 Primary

  Configuration of memory controller to different memory types · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F11/106

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title