Method and apparatus to reduce power consumption for refresh of memory devices on a memory module

Patent metadata

Field	Value
Publication number	US-11250902-B2
Application number	US-201916584724-A
Country	US
Kind code	B2
Filing date	Sep 26, 2019
Priority date	Sep 26, 2019
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.

First claim

What is claimed is:

1. A memory controller, comprising:
a Dynamic Random Access Memory (DRAM) interface to transfer data over a bus to a memory module, the memory module comprising at least two sub channels, each sub channel comprising a plurality of DRAM devices;
a first refresh mode register to store a first refresh rate for a first sub channel of the memory module;
a second refresh mode register to store a second refresh rate for a second sub channel of the memory module; and
a memory module refresh mode controller to modify the first refresh rate based a first temperature read from a first thermal sensor in the first sub channel of the memory module and to modify the second refresh rate based on a second temperature read from a second thermal sensor in the second sub channel of the memory module to refresh the plurality of DRAM devices in the first sub channel at the first refresh rate and to refresh the plurality of DRAM devices in the second sub channel at the second refresh rate, a difference between the first temperature and the second temperature is greater than 13° C.

2. The memory controller of claim 1 , wherein the first refresh rate is 1× refresh rate or 2× refresh rate.

3. The memory controller of claim 1 , wherein the first thermal sensor to couple to the memory controller via one of a standard I3C serial bus or System Management Bus (SMBus).

4. The memory controller of claim 1 , wherein the memory module refresh mode controller to periodically read a register in the first thermal sensor to determine if the first temperature is above a high temperature or below a low temperature, the first refresh rate is 2× refresh rate while the first temperature is above the high temperature.

5. The memory controller of claim 4 , wherein the low temperature is 85° C. or less and the high temperature is greater than 85° C.

6. The memory controller of claim 1 , wherein the DRAM interface is a double data rate (DDR) high-speed DRAM interface.

7. A method comprising:
transferring, by a Dynamic Random Access Memory (DRAM) interface, data over a bus to a memory module, the memory module comprising at least two sub channels, each sub channel comprising a plurality of DRAM devices;
storing, in a first refresh mode register, a first refresh rate for a first sub channel of the memory module;
storing in a second refresh mode register, a second refresh rate for a second sub channel of the memory module; and
modifying, by a memory module refresh mode controller, the first refresh rate based a first temperature read from a first thermal sensor in the first sub channel;
modifying, by the memory module refresh mode controller, the second refresh rate based on a second temperature read from a second thermal sensor in the second sub channel of the memory module; and
refreshing the plurality of DRAM devices in the first sub channel at the first refresh rate and the plurality of DRAM devices in the second sub channel at the second refresh rate, a difference between the first temperature and the second temperature is greater than 13° C.

8. The method of claim 7 , wherein the first refresh rate is 1× refresh rate or 2× refresh rate.

9. The method of claim 7 , further comprising:
accessing the first thermal sensor and the second thermal sensor via one of a standard I3C serial bus or System Management Bus (SMBus).

10. The method of claim 7 , further comprising:
periodically reading, by the memory module refresh mode controller, a register in the first thermal sensor to determine if the first temperature is above a high temperature or below a low temperature the first refresh rate is 2× refresh rate while the first temperature is above the high temperature.

11. The method of claim 10 , wherein the low temperature is 85° C. or less and the high temperature is greater than 85° C.

12. The method of claim 7 , wherein the DRAM interface is a double data rate (DDR) high-speed DRAM interface.

13. A system comprising:
a memory module comprising at least two sub channels, each sub channel comprising a plurality of Dynamic Random Access Memory (DRAM) devices;
a memory controller comprising:
a DRAM interface to transfer data over a bus to the memory module;
a first refresh mode register to store a first refresh rate for a first sub channel of the memory module;
a second refresh mode register to store a second refresh rate for a second sub channel of the memory module; and
a memory module refresh mode controller to modify the first refresh rate based a first temperature read from a first thermal sensor in the first sub channel of the memory module and to modify the second refresh rate based on a second temperature read from a second thermal sensor in the second sub channel of the memory module to refresh the plurality of DRAM devices in the first sub channel at the first refresh rate and to refresh the plurality of DRAM devices in the second sub channel at the second refresh rate, a difference between the first temperature and the second temperature is greater than 13° C.; and

a display communicatively coupled to a processor to display data stored in the DRAM devices.

14. The system of claim 13 , wherein the first refresh rate is 1× refresh rate or 2× refresh rate.

15. The system of claim 13 , wherein the first thermal sensor to couple to the memory controller via one of a standard I3C serial bus or System Management Bus (SMBus).

16. The system of claim 13 , wherein the memory module refresh mode controller to periodically read a register in the first thermal sensor to determine if the first temperature is above a high temperature or below a low temperature the first refresh rate is 2× refresh rate while the first temperature is above the high temperature.

17. The system of claim 16 , wherein the low temperature is 85° C. or less and the high temperature is greater than 85° C.

Assignees

• Intel Corp

Inventors

• Heymann Douglas
• Chen Wei P
• Chittor Suresh
• Vergis George

Classifications

• G01K13/00

  Thermometers specially adapted for specific purposes · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/40626 Primary

  Temperature related aspects of refresh operations · CPC title

• G06F1/3225 Primary

  of memory devices · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title