Processing system with interspersed processors DMA-FIFO
US-12197970-B2 · Jan 14, 2025 · US
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Bindloss Keith M patents
Bindloss Keith M is listed as an inventor on 23 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Bindloss Keith M |
| Total patents | 23 |
| First publication | Aug 23, 2016 |
| Latest publication | Jan 14, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory-network processor with programmable optimizations
US-11900124-B2 · Feb 13, 2024 · US
Memory network processor
US-11829320-B2 · Nov 28, 2023 · US
Memory-network processor with programmable optimizations
US-2023153117-A1 · May 18, 2023 · US
Memory Network Processor
US-2023061478-A1 · Mar 2, 2023 · US
Memory network processor
US-11550750-B2 · Jan 10, 2023 · US
Memory-network processor with programmable optimizations
US-11544072-B2 · Jan 3, 2023 · US
Processor instructions to accelerate FEC encoding and decoding
US-11327753-B2 · May 10, 2022 · US
Processing System With Interspersed Processors DMA-FIFO
US-2021326193-A1 · Oct 21, 2021 · US
Memory-network processor with programmable optimizations
US-2021208895-A1 · Jul 8, 2021 · US
Recent patents
Latest publications not already listed above.
Processing system with interspersed processors DMA-FIFO
US-11030023-B2 · Jun 8, 2021 · US
Memory-network processor with programmable optimizations
US-11016779-B2 · May 25, 2021 · US
Memory Network Processor
US-2021034566-A1 · Feb 4, 2021 · US
Processor Instructions to Accelerate FEC Encoding and Decoding
US-2020319880-A1 · Oct 8, 2020 · US
Memory network processor
US-10747709-B2 · Aug 18, 2020 · US
Processor instructions to accelerate FEC encoding and decoding
US-10691451-B2 · Jun 23, 2020 · US
Memory-Network Processor with Programmable Optimizations
US-2019369990-A1 · Dec 5, 2019 · US
Memory Network Processor
US-2019138492-A1 · May 9, 2019 · US
Processor Instructions to Accelerate FEC Encoding and Decoding
US-2017185399-A1 · Jun 29, 2017 · US
Processing System With Interspersed Processors DMA-FIFO
US-2016335207-A1 · Nov 17, 2016 · US
Memory-network processor with programmable optimizations
US-2016328231-A1 · Nov 10, 2016 · US
Memory-network processor with programmable optimizations
US-9430369-B2 · Aug 30, 2016 · US
Processing system with interspersed processors DMA-FIFO
US-9424213-B2 · Aug 23, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Coherent Logix Inc | 24 |
| Hyperx Logic Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| Y02D10/00 | 19 |
| G06F9/3885 | 12 |
| G06F9/3867 | 12 |
| G06F9/546 | 11 |
| G06F9/3005 | 8 |