Processor instructions to accelerate FEC encoding and decoding

Patent metadata

Field	Value
Publication number	US-11327753-B2
Application number	US-202016907715-A
Country	US
Kind code	B2
Filing date	Jun 22, 2020
Priority date	Dec 28, 2015
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.

First claim

What is claimed is:

1. A signal processing device, comprising:
a memory medium comprising program instructions for performing forward error correction (FEC) using an M-width add-sign instruction; and
a processing element configured to execute the program instructions, wherein the processing element includes an M-width data-processing pathway, wherein the M-width data-processing pathway is configured by the program instructions to execute an add-sign instruction, wherein the add-sign instruction specifies a first input operand including a first operand value and a second operand value, and a second input operand including a third operand value and a fourth operand value, wherein, in executing the add-sign instruction, the M-width data-processing pathway is configured to:
on a first respective clock cycle of a plurality of clock cycles:
determine a first signed value by applying a first sign function to the first operand value; and
determine a second signed value by applying a second sign function to the second operand value; and

on a second respective clock cycle of the plurality of clock cycles:
determine a first output value by adding the first signed value to the third operand value;
determine a second output value by adding the second signed value to the fourth operand value; and
store the first output value and the second output value.

2. The signal processing device of claim 1 , wherein the M-width add-sign instruction further specifies the first sign function and the second sign function.

3. The signal processing device of claim 1 , wherein the M-width add-sign instruction specifies the first input operand by specifying a memory location at which the first input operand is located, and wherein the M-width add-sign instruction specifies the second input operand by specifying a memory location at which the second input operands is located.

4. The signal processing device of claim 1 , wherein the M-width add-sign instruction further specifies a plural set of first input operands and a plural set of second input operands, wherein, in executing the add-sign instruction, the M-width data-processing pathway is configured to store a plural set of output values for the plural set of first input operands and the plural set of second input operands.

5. The signal processing device of claim 4 , further comprising a bit-packed register, wherein, in executing the M-width add-sign instruction, the M-width data-processing pathway is configured to:
store, in the bit-packed register, a plural set of first sign functions corresponding to a plural set of first operand values of the plural set of first input operands; and
store, in the bit-packed register, a plural set of second sign functions corresponding to a plural set of second operand values of the plural set of first input operands.

6. The signal processing device of claim 4 , wherein the M-width data-processing pathway is considered a first M-width data-processing pathway, the processing element further comprising:
a second M-width data-processing pathway, wherein the second dual data-processing pathway is configured in the same manner as the first M-width data-processing pathway.

7. The signal processing device of claim 1 , wherein, in response to receiving an M-width instruction other than the add-sign instruction, the M-width data-processing pathway is reconfigured to perform a plurality of data-processing operations other than those configured for performing the add-sign instruction.

8. A signal processing device, comprising:
a memory medium comprising program instructions for performing forward error correction (FEC) using M-width instructions; and
a processing element configured to execute the program instructions, wherein the processing element includes an M-width data-processing pathway, wherein the M-width data-processing pathway is dynamically configured by the program instructions to execute an M-width instruction,
wherein, in response to receiving an M-width sign instruction, the M-width sign instruction comprising an input operand including M operand values, and a sign operand including M sign functions, the M-width data-processing pathway is configured to, on a single clock cycle:
produce M output values by applying a respective sign function of the sign operand to each operand value of the input operand; and

wherein, in response to receiving an M-width instruction other than the M-width sign instruction, the M-width data-processing pathway is configured to perform a plurality of data-processing operations other than those configured in response to receiving the M-width sign instruction.

9. The signal processing device of claim 8 , wherein the M-width sign instruction specifies the input operand by specifying a memory location at which the input operand is located, and wherein the M-width sign instruction specifies the sign operand by specifying a memory location at which the sign operand is located.

10. The signal processing device of claim 8 , wherein, in response to receiving the M-width sign instruction, the M-width data-processing pathway is further configured to store the M output values on the first clock cycle.

11. The signal processing device of claim 8 , wherein the M-width data-processing pathway is considered a first M-width data-processing pathway, the processing element further comprising:
a second M-width data-processing pathway, wherein the second M-width data-processing pathway is configured in the same manner as the first M-width data-processing pathway.

12. The signal processing device of claim 8 , wherein the M-width instruction other than the M-width sign instruction is an M-width add-sign instruction for performing FEC.

13. A processing element, comprising:
a pipelined series of M-width operational stages configurable to implement an M-width instruction for performing forward error correction (FEC), each operational stage comprising:
an input select module configurable to pass one or more input values dynamically selected from a plurality of input values, based on the M-width instruction;
M parallel operational modules, each of the operational modules configurable to:
receive from the input select module at least a subset of the one or more selected input values; and
produce a result value by performing a dynamically configured operation on the received input values, wherein the operation is configured based on the M-width instruction; and

one or more output registers configurable to store the result values;

wherein the one or more output registers of each operational stage prior to the final operational stage provide input values to the input select module of the subsequent stage in the series of operational stages.

14. The processing element of claim 13 , further comprising an output select module configured based on the M-width instruction to select at least one output of the one or more output registers of the final operational stage as an output value of the processing element.

15. The processing element of claim 13 , wherein each operational module produces the respective result value by performing the dynamically configured operation within a single clock cycle.

16. The processing element of claim 13 , wherein the one or more output registers of at least one of the operational stages is further configurable to store one or more values received directly from the respective input select module of operational stage.

17. The processing element of claim 16 , wherein, in response to receiving a particular M-width instruction, the M parallel operational modules of a p

Assignees

• Coherent Logix Inc

Inventors

• Bindloss Keith M
• Dobbs Carl S
• Mezhibovsky Evgeny
• Raza Zahir
• Shelby Kevin A

Classifications

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/3867

  using instruction pipelines · CPC title